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Process Technology - DEC
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Revision as of 18:22, 11 June 2017 by David (talk | contribs) (Timeline)

This article details details DEC's Semiconductor Process Technology history for research and posterity.

The table below shows the history of DEC's process scaling. Values were taken from various DEC documents including historical presentations and journals, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between DEC's own documents and therefore discrepancies may exist.

Timeline

YearProcessNodeMLayersµarchsAttributes
1984 ZMOS 3 µm 2 V-11,
MicroVAX II
Tox43 nm
Lg3 µm
1986 CMOS-1 2 µm 2 Tox
Lg2 µm
1988 CMOS-2 1.5 µm 2 Tox
Lg1.5 µm
1990 CMOS-3 1 µm 2 Tox
Lg1 µm
1991 CMOS-4 0.75 µm 3 NVAX,
Alpha 21064
Tox10.5 nm
Vdd3.3 VSRAM100 µm²
Lg0.75 µmLeff0.50 µm
1996 CMOS-4S 0.675 µm 3 NVAX,
NVAX+
Tox
1994 CMOS-5 0.5 µm 4 NVAX++Tox
1996 CMOS-6 0.35 µm 4 Tox
1997 CMOS-7 0.25 µm 5 Tox
1997Fab-6 in Hudson, Mass was sold to Intel which consequently upgraded it for $800M to Intel's propiatery 0.18 µm (see Intel's Process).
2013In late 2013 Intel announced that it will be closing the Hudson Fab due to no longer meeting their requirements such as aging technology.