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Difference between revisions of "dec/microarchitectures/strongarm"
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(Created page with "{{dec title|StrongARM|arch}} {{microarchitecture |atype=CPU |name=StrongARM |designer=DEC |designer 2=ARM Holdings |manufacturer=DEC }}")
 
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|designer 2=ARM Holdings
 
|designer 2=ARM Holdings
 
|manufacturer=DEC
 
|manufacturer=DEC
 +
|introduction=February 5, 1996
 +
|process=0.35 µm
 +
|cores=1
 +
|oooe=No
 +
|speculative=No
 +
|renaming=No
 +
|stages=5
 +
|decode=1-way
 +
|isa=ARMv4
 +
|l1i=16 KiB
 +
|l1i per=core
 +
|l1i desc=32-way set associative
 +
|l1d=16 KiB
 +
|l1d per=core
 +
|l1d desc=32-way set associative
 +
|successor=XScale
 +
|successor link=intel/microarchitectures/xscale
 
}}
 
}}

Revision as of 15:25, 29 May 2017

Edit Values
StrongARM µarch
General Info
Arch TypeCPU
DesignerDEC, ARM Holdings
ManufacturerDEC
IntroductionFebruary 5, 1996
Process0.35 µm
Core Configs1
Pipeline
OoOENo
SpeculativeNo
Reg RenamingNo
Stages5
Decode1-way
Instructions
ISAARMv4
Cache
L1I Cache16 KiB/core
32-way set associative
L1D Cache16 KiB/core
32-way set associative
Succession
codenameStrongARM +
core count1 +
designerDEC + and ARM Holdings +
first launchedFebruary 5, 1996 +
full page namedec/microarchitectures/strongarm +
instance ofmicroarchitecture +
instruction set architectureARMv4 +
manufacturerDEC +
microarchitecture typeCPU +
nameStrongARM +
pipeline stages5 +
process350 nm (0.35 μm, 3.5e-4 mm) +