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Latest revision Your text
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** L1 Data Cache
 
** L1 Data Cache
 
*** 16 KiB, 32-way set associative
 
*** 16 KiB, 32-way set associative
*** Write-back policy
 
 
** No L2 cache
 
** No L2 cache
  
 
* TLB
 
* TLB
** ITLB
+
** 32-entry, fully associative
*** 32-entry, fully associative
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** Each entry can map 4 KiB small pages, 64 KiB large pages, and 1 MiB sections
*** Each entry can map 4 KiB, 64 KiB, and 1 MiB pages
 
** DTLB
 
*** 32-entry, fully associative
 
*** Each entry can map 4 KiB, 64 KiB, and 1 MiB pages
 
  
 
== Die ==
 
== Die ==

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codenameStrongARM +
core count1 +
designerDEC + and ARM Holdings +
first launchedFebruary 5, 1996 +
full page namedec/microarchitectures/strongarm +
instance ofmicroarchitecture +
instruction set architectureARMv4 +
manufacturerDEC + and Intel +
microarchitecture typeCPU +
nameStrongARM +
pipeline stages5 +
process350 nm (0.35 μm, 3.5e-4 mm) +