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== Process Technology ==
 
== Process Technology ==
 
{{see also|0.35 µm process}}
 
{{see also|0.35 µm process}}
Alpha 21264 was manufactured on a [[0.35 µm process]] at DEC's own Hudson foundry. The process had a 0.35 µm drawn gate length and 0.25 µm effective channel length. The CMOS process had 3 metal layers. The chip allowed for a supply voltage of up to 2 V in order to limit the chips to a power limit of 72 W, although it was actually designed to reliably operate at up to 2.5 V.
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Alpha 21264 was manufactured on a [[0.35 µm process]] at DEC's own Hudson foundry. The process had a 0.35 µm drawn gate length and 0.25 µm effective channel length. The CMOS process had 3 metal layers and allowed for a supply voltage limited to 2 V in order to limit the chips to a power limit of 72 W, although it was actually designed to reliably operate at up to 2.5 V.
  
 
== Architecture ==
 
== Architecture ==

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codenameAlpha 21264 +
core count1 +
designerDEC +
first launchedFebruary 1998 +
full page namedec/microarchitectures/alpha 21264 +
instance ofmicroarchitecture +
instruction set architectureAlpha +
manufacturerDEC +, Intel + and Samsung +
microarchitecture typeCPU +
nameAlpha 21264 +
pipeline stages6 +
process350 nm (0.35 μm, 3.5e-4 mm) +