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From WikiChip
Alpha 21064 - Microarchitectures - DEC
< dec
| Edit Values | |
| Alpha 21064 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | DEC |
| Manufacturer | DEC |
| Introduction | November 20 1992 |
| Process | 0.75 µm, 0.675 µm |
| Core Configs | 1 |
| Pipeline | |
| Type | Superscalar |
| OoOE | No |
| Speculative | Yes |
| Reg Renaming | No |
| Stages | 7-12 |
| Decode | 2-way |
| Instructions | |
| ISA | Alpha |
| Cache | |
| L1I Cache | 8 KiB/core direct-mapped |
| L1D Cache | 8 KiB/core direct-mapped |
| L2 Cache | 0.125-16 MiB/motherboard |
| Succession | |
Alpha 21064 was the first Alpha microarchitecture designed by DEC and introduced in 1992.
Retrieved from "https://en.wikichip.org/w/index.php?title=dec/microarchitectures/alpha_21064&oldid=44651"
Facts about "Alpha 21064 - Microarchitectures - DEC"
| codename | Alpha 21064 + |
| core count | 1 + |
| designer | DEC + |
| first launched | November 20, 1992 + |
| full page name | dec/microarchitectures/alpha 21064 + |
| instance of | microarchitecture + |
| instruction set architecture | Alpha + |
| manufacturer | DEC + |
| microarchitecture type | CPU + |
| name | Alpha 21064 + |
| pipeline stages (max) | 12 + |
| pipeline stages (min) | 7 + |
| process | 750 nm (0.75 μm, 7.5e-4 mm) + and 675 nm (0.675 μm, 6.75e-4 mm) + |
