Editing coremark-mhz

{{title|CoreMark/MHz}}
'''CoreMark/MHz''' is a measurement of [[single thread performance]] per [[clock frequency]] based on the [[CoreMark]] [[benchmark]].

== Overview ==
'''CoreMark/MHz''' is a measurement of [[single thread performance]] per [[clock frequency]]. The number is based on the [[CoreMark]] [[benchmark]] score. It is obtained by taking the single-core [[CoreMark]] number and dividing it by the [[clock speed]] used when the benchmark is performed.

While CoreMark is a relatively simple benchmark that addresses some of the deficiencies with [[Dhrystone]], it has been designed around embedded applications and therefore demonstrates highly favorable numbers for relatively simple designs (e.g., [[dual-issue]] [[in-order]]) while having weaker performance scaling in complex designs (e.g., [[out-of-order]] [[superscalar]]). Therefore it may sometimes show that a very well-design in-order core achieves >80% the performance of very complex high-performance OoO cores while real-world applications will demonstratively show significantly bigger gaps and discrepancies. Additionally, since the score is normilized by [[clock frequency]], it cannot be used to derived absolute performances. Furthermore, since it's possible to achieve higher CoreMark at considerably lower frequency through well-known techniques such as shortening the pipeline which saves significant amount of silicon, using CoreMark/MHz per unite area to derive area-efficiency is problematic.

== Scores ==
Note that some values were taken as reported by the chip designers while other values were calculated by WikiChip.

{| class="wikitable sortable"
|-
! Designer !! Microarchitecture !! Intro !! [[ISA]] !! CoreMark/MHz 
|-
| [[Arm]] || {{armh|Cortex-M55|l=arch}} || February 10, 2020 || {{arm|ARMv8.1-M}} Mainline, FPU, {{arm|Helium}} || 4.2
|-
| [[Arm]] || {{armh|Cortex-M7|l=arch}} ||  || {{arm|ARMv7-M}}, FPU || 5.01
|-
| [[Arm]] || {{armh|Cortex-M35P|l=arch}} ||  || {{arm|ARMv8-M}} Mainline, FPU || 4.02
|-
| [[Arm]] || {{armh|Cortex-M33|l=arch}} ||  || {{arm|ARMv8-M}} Mainline, FPU || 4.02
|-
| [[Arm]] || {{armh|Cortex-M4|l=arch}} ||  || {{arm|ARMv7-M}}, FPU || 3.42
|-
| [[Arm]] || {{armh|Cortex-M3|l=arch}} ||  || {{arm|ARMv7-M}} || 3.34
|-
| [[Arm]] || {{armh|Cortex-M23|l=arch}} ||  || {{arm|ARMv8-M}} Mainline || 2.64
|-
| [[OnChip]] || [[Apicalis]] ||  || {{riscv|RV32IM}} || 2.7
|-
| [[Arm]] || {{armh|Cortex-M1|l=arch}} ||  || {{arm|ARMv6-M}} || 1.85
|-
| [[Arm]] || {{armh|Cortex-M0+|l=arch}} ||  || {{arm|ARMv6-M}} || 2.46
|-
| [[Arm]] || {{armh|Cortex-M0|l=arch}} ||  || {{arm|ARMv6-M}} || 2.33
|-
| [[Arm]] || {{armh|Cortex-R4|l=arch}} ||  || {{arm|ARMv7-R}} || 3.47
|-
| [[Arm]] || {{armh|Cortex-R5|l=arch}} ||  || {{arm|ARMv7-R}} || 3.47
|-
| [[Arm]] || {{armh|Cortex-R7|l=arch}} ||  || {{arm|ARMv7-R}} || 4.62
|-
| [[Arm]] || {{armh|Cortex-R8|l=arch}} ||  || {{arm|ARMv7-R}} || 4.62
|-
| [[Arm]] || {{armh|Cortex-R52|l=arch}} ||  || {{arm|ARMv8-R}} || 4.2
|-
| [[Arm]] || {{armh|Cortex-R82|l=arch}} ||  || {{arm|ARMv8-R}} || 5.82
|-
| [[SiFive]] || {{sifive|E20|l=arch}} || || {{riscv|RV32IMC}} || 2.51
|-
| [[SiFive]] || {{sifive|E21|l=arch}} || || {{riscv|RV32IMAC}} || 3.1
|-
| [[SiFive]] || {{sifive|E24|l=arch}} || || {{riscv|RV32IMAFC}} || 3.1
|-
| [[SiFive]] || {{sifive|U74|l=arch}} || || {{riscv|RV64GC}} || 5.1
|-
| [[SiFive]] || {{sifive|U54|l=arch}} || || {{riscv|RV64GC}} || 3.01
|-
| [[SiFive]] || {{sifive|E31|l=arch}} || || {{riscv|RV32IMAC}} || 3.01
|-
| [[SiFive]] || {{sifive|E76|l=arch}} || || {{riscv|RV32IMAFC}} || 5.1
|-
| [[SiFive]] || {{sifive|S76|l=arch}} || || {{riscv|RV64GC}} || 5.1
|-
| [[SiFive]] || {{sifive|E34|l=arch}} || || {{riscv|RV32IMAFC}} || 3.01
|-
| [[SiFive]] || {{sifive|S54|l=arch}} || || {{riscv|RV64IMAFDC}} || 3.01
|-
| [[UC Berkeley]] || {{ucberkeley|BOOMv2|l=arch}} (2-way) || || {{riscv|RV64IMAFD}} || 3.92
|-
| [[UC Berkeley]] || {{ucberkeley|BOOMv2|l=arch}} (4-way) || || {{riscv|RV64IMAFD}} || 4.7
|-
| [[Western Digital]] || [[SweRV EH1]] || || {{riscv|RV32IMC}} || 5.78
|-
| [[Western Digital]] || [[SweRV EH2 single thread]] || || {{riscv|RV32IMC}} || 6.03
|-
| [[Western Digital]] || [[SweRV EH2 two threads]] || || {{riscv|RV32IMAC}} || 7.83
|-
| [[Western Digital]] || [[SweRV EL2]] || || {{riscv|RV32IMC}} || 4.33
|-
| [[Alibaba]] || [[XT910]] || July 25, 2019 || {{riscv|RV64GCV}} || 7.1
|}

== See also ==
* [[Dhrystone]] [[DMIPS/MHz]]
* [[Whetstone]] [[WMIPS/MHz]]