Semiconductor & Computer Engineering
(inverter example) |
|||
| Line 3: | Line 3: | ||
== Overview == | == Overview == | ||
| − | CMOS primarily makes use of what would otherwise be two | + | {{main|/complementary topology|l1=CMOS Complementary Topology}} |
| + | CMOS primarily makes use of what would otherwise be two separate circuit technologies - [[pmos transistor|pMOS]] and [[nMOS transistor|nMOS]]. To better understand this, consider an [[nMOS transistor]]. Because it can pull no higher than V<sub>DD</sub> - V<sub>t</sub> we get a degraded 1 output. Likewise with pMOS, we can pull no lower than V<sub>t</sub> - a degraded 0 output. By combining both types, we can borrow the desired characteristics from both transistors such as a strong 0 and a strong 1. | ||
| + | |||
| + | === Inverter Example === | ||
| + | {{main|inverter}} | ||
| + | The simplest gate that can be implemented is the [[NOT gate]] which simply inverts the input. We can implement an inverter using a single nMOS and pMOS transistors. The pMOS transistor is connected to V<sub>DD</sub> while the nMOS transistor is connected to GND. When ''A'' is 0, the nMOS transistor turns OFF and the pMOS transistor turns ON. This results in ''Q'' being pulled up to 1 since the pMOS transistor will conduct V<sub>DD</sub>. Conversely, when ''A'' is 1, the nMOS transistor turns ON and the pMOS transistor turns OFF, thereby pulling ''Q'' down to GND. | ||
{{stub}} | {{stub}} | ||
[[Category:CMOS]] | [[Category:CMOS]] | ||
Revision as of 18:24, 15 November 2015
CMOS (Complementary metal–oxide–semiconductor) is a technique for constructing digital logic circuits from two complementary MOS transistors - pMOS and nMOS. CMOS is the dominant technology used for VLSI and ULSI circuit chips used for anywhere from SRAM to microcontrollers and microprocessors.
Overview
- Main article: CMOS Complementary Topology
CMOS primarily makes use of what would otherwise be two separate circuit technologies - pMOS and nMOS. To better understand this, consider an nMOS transistor. Because it can pull no higher than VDD - Vt we get a degraded 1 output. Likewise with pMOS, we can pull no lower than Vt - a degraded 0 output. By combining both types, we can borrow the desired characteristics from both transistors such as a strong 0 and a strong 1.
Inverter Example
- Main article: inverter
The simplest gate that can be implemented is the NOT gate which simply inverts the input. We can implement an inverter using a single nMOS and pMOS transistors. The pMOS transistor is connected to VDD while the nMOS transistor is connected to GND. When A is 0, the nMOS transistor turns OFF and the pMOS transistor turns ON. This results in Q being pulled up to 1 since the pMOS transistor will conduct VDD. Conversely, when A is 1, the nMOS transistor turns ON and the pMOS transistor turns OFF, thereby pulling Q down to GND.
 |
This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information. |
