Semiconductor & Computer Engineering
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Chiplets refer to the independent constituents which make up a large chip built out of multiple smaller dies. Historically the need to go with multiple chips was driven by the [[reticle limit]] which dictated the maximum size of chip possible to be [[fabricated]]. Designs that exceeded the reticle limit had to be split up into smaller dies in order to be manufacturable. More recently, the desire to move to a chiplet-based designed has been driven by the increasing cost of manufacturing devices on leading-edge process nodes. Due to the cost associated with leading-edge nodes, it became advantageous to break down a large die into smaller 'chiplets' in order to improve [[yield]] and [[binning]]. | Chiplets refer to the independent constituents which make up a large chip built out of multiple smaller dies. Historically the need to go with multiple chips was driven by the [[reticle limit]] which dictated the maximum size of chip possible to be [[fabricated]]. Designs that exceeded the reticle limit had to be split up into smaller dies in order to be manufacturable. More recently, the desire to move to a chiplet-based designed has been driven by the increasing cost of manufacturing devices on leading-edge process nodes. Due to the cost associated with leading-edge nodes, it became advantageous to break down a large die into smaller 'chiplets' in order to improve [[yield]] and [[binning]]. | ||
| + | === Motivation === | ||
| + | [[File:amd iedm 2017 dr lisa su keynote 7nm cost.png|thumb|right|At IEDM 2017, AMD CEO Dr. Lisa Su reported cost per yielded mm² for a 250 mm² die.]] | ||
| + | As the industry moves to smaller [[process nodes]], costs for yielding large dies continues to increase. Compared to 250 mm² [[die]] on the [[45 nm process]], the [[16 nm process]] more than doubles the cost/mm² and the [[7 nm process]] nearly double that to 4x the cost per yielded mm². Moving to the [[5 nm]] and even [[3 nm]] nodes, the cost is expected to continue to increase. Fabricating large monolithic dies will becomes increasingly less economical. One solution to easing the economics of manufacturing chips with a large amount of [[transistors]], the industry has started shifting to chiplet-based design whereby a single chip is broken down into multiple smaller chiplets. | ||
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| + | Consider a [[D0]] of 0.1 defects per cm². Below is a plot of percent of [[yield]] per wafer for a die of various sizes versus the same die consisting of two, three, and four chiplets. Note that an additional 10% overhead for the cross-die communication has been added to the chiplet-based design. | ||
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| + | :[[File:monolithic design vs chiplet yield.png|800px]] | ||
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| + | == Bibliography == | ||
| + | * IEDM 2017, Dr. Lisa Su. Keynote presentation. | ||
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Revision as of 16:10, 28 January 2019
A chiplet is an integrated circuit block that is part of a chip that consists of multiple such chiplets. In such chips, a system is subdivided into functional circuit blocks, called "chiplets", that are often reusable IP blocks.
Overview
Chiplets refer to the independent constituents which make up a large chip built out of multiple smaller dies. Historically the need to go with multiple chips was driven by the reticle limit which dictated the maximum size of chip possible to be fabricated. Designs that exceeded the reticle limit had to be split up into smaller dies in order to be manufacturable. More recently, the desire to move to a chiplet-based designed has been driven by the increasing cost of manufacturing devices on leading-edge process nodes. Due to the cost associated with leading-edge nodes, it became advantageous to break down a large die into smaller 'chiplets' in order to improve yield and binning.
Motivation
As the industry moves to smaller process nodes, costs for yielding large dies continues to increase. Compared to 250 mm² die on the 45 nm process, the 16 nm process more than doubles the cost/mm² and the 7 nm process nearly double that to 4x the cost per yielded mm². Moving to the 5 nm and even 3 nm nodes, the cost is expected to continue to increase. Fabricating large monolithic dies will becomes increasingly less economical. One solution to easing the economics of manufacturing chips with a large amount of transistors, the industry has started shifting to chiplet-based design whereby a single chip is broken down into multiple smaller chiplets.
Consider a D0 of 0.1 defects per cm². Below is a plot of percent of yield per wafer for a die of various sizes versus the same die consisting of two, three, and four chiplets. Note that an additional 10% overhead for the cross-die communication has been added to the chiplet-based design.
Bibliography
- IEDM 2017, Dr. Lisa Su. Keynote presentation.
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