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== Overview == | == Overview == | ||
[[File:cha soc overview.svg|thumb|right|CHA Overview]] | [[File:cha soc overview.svg|thumb|right|CHA Overview]] | ||
− | Announced in 2019 and expected to be introduced in 2020, '''CHA''' (pronounced ''C-H-A'') is a new ground-up [[x86]] SoC designed by [[Centaur]] for the server, edge, and AI market. Fabricated on TSMC [[16 nm process]], the chip integrates eight high-performance [[x86]] "CNS" cores along with a brand new clean-sheet design "NCORE" [[neural processor]]. | + | Announced in 2019 and expected to be introduced in 2020, '''CHA''' (pronounced ''C-H-A'') is a new ground-up [[x86]] SoC designed by [[Centaur]] for the server, edge, and AI market. Fabricated on TSMC [[16 nm process]], the chip integrates eight high-performance [[x86]] "CNS" cores along with a brand new clean-sheet design high-performance "NCORE" [[neural processor]]. This is the first server x86 chip to integrate an AI [[accelerator]]. The integrated NPU is designed to allow for a reduction of platform cost by offering an AI inference coprocessor "free" on-die along with the standard server-class x86 cores. For many workloads, this accelerator means it's no longer required to add a third-party PCIe-based [[accelerator card]] unless a considerably higher performance is required. |
− | + | The CHA SoC features new CNS cores which introduce considerably higher [[single-thread performance]]. The cores also introduce the {{x86|AVX-512}} extension in order to offer better performance and more flexibility. | |
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+ | CHA is a fully integrated SoC. It incorporates both the [[source bridge]] and [[north bridge]] on-die. The chip supports for up to quad-channel [[DDR4 memory]] and up to 44 PCIe Gen 3 lanes. Additionally, the southbridge provides all the usual legacy I/O functionality. Additionally, CHA supports the ability to directly link to a second CHA SoC in a 2-way [[multiprocessing]] configuration. All the cores, along with the NCORE, the southbridge, and memory controller are all [[ring interconnect|interconnected on a ring]]. | ||
== CNS Core == | == CNS Core == |
Facts about "CHA - Microarchitectures - Centaur Technology"
codename | CHA + |
core count | 8 + |
designer | Centaur Technology + |
full page name | centaur/microarchitectures/cha + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | CHA + |
pipeline stages (max) | 22 + |
pipeline stages (min) | 20 + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |