Semiconductor & Computer Engineering
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Information for "cea-leti/microarchitectures/tsarlet"
Basic information
| Display title | TSARLET - Microarchitectures - CEA Leti |
| Default sort key | cea-leti/microarchitectures/tsarlet |
| Page length (in bytes) | 12,420 |
| Page ID | 35948 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 2 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 02:00, 29 February 2020 |
| Latest editor | 132.166.183.104 (talk) |
| Date of latest edit | 10:17, 27 March 2020 |
| Total number of edits | 21 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (9) | Templates used on this page: |
Facts about "TSARLET - Microarchitectures - CEA Leti"
| codename | TSARLET + |
| core count | 96 + |
| designer | CEA-Leti + |
| full page name | cea-leti/microarchitectures/tsarlet + |
| instance of | microarchitecture + |
| instruction set architecture | MIPS32v1 + |
| manufacturer | STMicroelectronics + |
| microarchitecture type | CPU + |
| name | TSARLET + |
| pipeline stages | 5 + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + and 65 nm (0.065 μm, 6.5e-5 mm) + |
