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== Overview ==
 
== Overview ==
CCIX is a high-performance, low latency, chip-to-chip [[interconnect architecture]] that provides a cache coherent framework for [[heterogeneous system architecture]]s. Cache coherency is automatically maintained at all time between the [[central processing unit]] and the various other [[accelerators]] in the system. CCIX supports signaling rates between 16 GT/s and 25 GT/s per link with support for link aggregation for higher performance.
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CCIX is a high-performance, low latency, chip-to-chip [[interconnect architecture]] that provides a cache coherent framework for [[heterogeneous system architecture]]s. Cache coherency is automatically maintained at all time between the [[central processing unit]] and the various other [[accelerators]] in the system. CCIX supports signaling rates between 16 GT/s and 25 GT/s per link with support for port aggregation for higher performance.
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Every CCIX-support device incorporates at least a single CCIX port which is pin-compatible with any other CCIX-enabled device. CCIX supports a large set of topologies such as chip-to-chip, chip-switch-chip, mesh, daisy chains, and rings.
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== Architecture ==
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CCIX is largely an extension of the [[PCI Express]] architecture, consists of a number of stacked protocol layers.
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* CCIX Protocol Layer - coherency protocol that manages memory reads and writes, provides a mapping for the on-chip architecture-dependent coherency protocols (e.g., AMBA CHI/ACE). This layer also defines the cache state (e.g. shared/unique, [[clean]]]/[[dirty]]).
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* CCIX Link Layer - formatting protocol for transport (e.g., [[PCIe]]). This layer also manages link aggregation.
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* CCIX Transport Specification
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** PCIe Transaction Layer - Handles PCIe transactions. The layer also supports virtual channels, permitting transmission for different data streams across a single shared link.
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** CCIX Transaction Layer - Handles CCIX transactions. This layer optimizes out superfluous PCIe [[packet]] fields, reducing overhead.
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* PCIe Data Link Layer - Handles standard [[data link layer]] (e.g., CRC, ACK).
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* CCIX/PCIe Physical Layer - Handles standard [[PCIe]] [[physical layer]]. This layer also supports 25 GT/s ESM mode.
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== Bibliography ==
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* CCIX Consortium. [https://docs.wixstatic.com/ugd/0c1418_c6d7ec2210ae47f99f58042df0006c3d.pdf ''An Introduction to CCIX: White Paper''].
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* CCIX Consortium. (2018, June 18). [https://www.businesswire.com/news/home/20180618005233/en/CCIX™-Consortium-Enables-Generation-Compute-Architectures-Availability ''CCIX™ Consortium Enables Next Generation Compute Architectures with the Availability of Base Specification 1.0''] [Press release].

Revision as of 22:09, 4 August 2018

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Cache Coherent Interconnect for Accelerators (CCIX), pronounced "see-six", is an open cache coherent interconnect architecture developed by the CCIX Consortium.

Overview

CCIX is a high-performance, low latency, chip-to-chip interconnect architecture that provides a cache coherent framework for heterogeneous system architectures. Cache coherency is automatically maintained at all time between the central processing unit and the various other accelerators in the system. CCIX supports signaling rates between 16 GT/s and 25 GT/s per link with support for port aggregation for higher performance.

Every CCIX-support device incorporates at least a single CCIX port which is pin-compatible with any other CCIX-enabled device. CCIX supports a large set of topologies such as chip-to-chip, chip-switch-chip, mesh, daisy chains, and rings.

Architecture

CCIX is largely an extension of the PCI Express architecture, consists of a number of stacked protocol layers.

  • CCIX Protocol Layer - coherency protocol that manages memory reads and writes, provides a mapping for the on-chip architecture-dependent coherency protocols (e.g., AMBA CHI/ACE). This layer also defines the cache state (e.g. shared/unique, clean]/dirty).
  • CCIX Link Layer - formatting protocol for transport (e.g., PCIe). This layer also manages link aggregation.
  • CCIX Transport Specification
    • PCIe Transaction Layer - Handles PCIe transactions. The layer also supports virtual channels, permitting transmission for different data streams across a single shared link.
    • CCIX Transaction Layer - Handles CCIX transactions. This layer optimizes out superfluous PCIe packet fields, reducing overhead.
  • PCIe Data Link Layer - Handles standard data link layer (e.g., CRC, ACK).
  • CCIX/PCIe Physical Layer - Handles standard PCIe physical layer. This layer also supports 25 GT/s ESM mode.

Bibliography