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Information for "cavium/thunderx2"

Basic information

Display titleThunderX2 - Cavium
Default sort keyThunderX2, Cavium
Page length (in bytes)3,866
Page ID30247
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page5
Counted as a content pageYes
Number of subpages of this page6 (0 redirects; 6 non-redirects)

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Edit history

Page creatorAt32Hz (talk | contribs)
Date of page creation00:55, 4 June 2018
Latest editor50.233.219.101 (talk)
Date of latest edit12:57, 4 December 2018
Total number of edits9
Total number of distinct authors4
Recent number of edits (within past 90 days)2
Recent number of distinct authors1

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Facts about "ThunderX2 - Cavium"
designerCavium +
first announcedMay 30, 2016 +
first launchedMay 7, 2018 +
full page namecavium/thunderx2 +
instance ofmicroprocessor family +
instruction set architectureARMv8 +
main designerCavium +
manufacturerTSMC +
microarchitectureThunderX2 + and Vulcan +
nameThunderX2 +
process14 nm (0.014 μm, 1.4e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +