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* '''Mem:''' Up to 2 TiB of quad/hexa/octa- channel DDR4 2666 MT/s memory | * '''Mem:''' Up to 2 TiB of quad/hexa/octa- channel DDR4 2666 MT/s memory | ||
** Up to 4 TiB in dual-socket configuration | ** Up to 4 TiB in dual-socket configuration | ||
− | * '''ISA:''' [[ | + | * '''ISA:''' [[ARMv8]], 128-bit {{arm|NEON}} SIMD |
* '''I/O:''' x48, x56 PCIe Gen 3 Lanes | * '''I/O:''' x48, x56 PCIe Gen 3 Lanes | ||
* Only the [[arm/aarch64 | 64-bit AArch64]] execution state is support. No [[arm/aarch32 | 32-bit AArch32]] support. | * Only the [[arm/aarch64 | 64-bit AArch64]] execution state is support. No [[arm/aarch32 | 32-bit AArch32]] support. |
Facts about "ThunderX2 - Cavium"
designer | Cavium + |
first announced | May 30, 2016 + |
first launched | May 7, 2018 + |
full page name | cavium/thunderx2 + |
instance of | microprocessor family + |
instruction set architecture | ARMv8.1 + |
main designer | Cavium + |
manufacturer | TSMC + |
microarchitecture | ThunderX2 + and Vulcan + |
name | ThunderX2 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |