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| first announced  = May 30, 2016
 
| first announced  = May 30, 2016
 
| first launched    = May 7, 2018
 
| first launched    = May 7, 2018
| isa              = ARMv8.1
+
| isa              = ARMv8
 
| microarch        = ThunderX2
 
| microarch        = ThunderX2
 
| microarch 2      = Vulcan
 
| microarch 2      = Vulcan
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| predecessor      = ThunderX
 
| predecessor      = ThunderX
 
| predecessor link = cavium/thunderx
 
| predecessor link = cavium/thunderx
| successor        = ThunderX3
+
| successor        =  
| successor link  = marvell/thunderx3
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| successor link  =  
 
}}
 
}}
 
'''ThunderX2''' is a family of {{arch|64}} [[multi-core]] [[ARM]] server microprocessors introduced by [[Cavium]] in early [[2018]] succeeding the original {{\\|ThunderX}} line.
 
'''ThunderX2''' is a family of {{arch|64}} [[multi-core]] [[ARM]] server microprocessors introduced by [[Cavium]] in early [[2018]] succeeding the original {{\\|ThunderX}} line.
  
 
== Overview ==
 
== Overview ==
The ThunderX2 was designed to succeed the original {{\\|ThunderX}} family. [[Cavium]] first announced the ThunderX2 back in May 30 2016 with models based on their own {{cavium|thunderx2|second-generation|l=arch}} microarchitecture with models up to 54 cores. Cavium focused the {{\\|ThunderX}} design on the networking space as the {{\\|Octeon TX}} family, and in late 2016 they acquired the {{cavium|Vulcan|l=arch}} design from [[Broadcom]] which has designed a server microprocessor but has given up on the project for reasons not well understood. In early 2018, Cavium announced that their ThunderX2 processors (now based on {{cavium|Vulcan|l=arch}}) have reached general availability.
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The ThunderX2 was designed to succeed the original {{\\|ThunderX}} family. [[Cavium]] first announced the ThunderX2 back in May 30 2016 with models based on their own {{cavium|thunderx2|second-generation|l=arch}} microarchitecture with models up to 54 cores. Cavium eventually scrapped their own design and in late 2016 they acquired the {{cavium|Vulcan|l=arch}} design from [[Broadcom]] which has designed a server microprocessor but has given up on the project for reasons not well understood. In early 2018, Cavium announced that their ThunderX2 processors (now based on {{cavium|Vulcan|l=arch}}) have reached general availability.
  
 
== Models ==
 
== Models ==
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* '''Mem:''' Up to 2 TiB of quad/hexa/octa- channel DDR4 2666 MT/s memory
 
* '''Mem:''' Up to 2 TiB of quad/hexa/octa- channel DDR4 2666 MT/s memory
 
** Up to 4 TiB in dual-socket configuration
 
** Up to 4 TiB in dual-socket configuration
* '''ISA:''' [[arm|ARMv8.1]], 128-bit {{arm|NEON}} SIMD
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* '''ISA:''' [[ARMv8]], 128-bit {{arm|SVE}}
 
* '''I/O:''' x48, x56 PCIe Gen 3 Lanes
 
* '''I/O:''' x48, x56 PCIe Gen 3 Lanes
* Only the [[arm/aarch64 | 64-bit AArch64]] execution state is support. No [[arm/aarch32 | 32-bit AArch32]] support.
 
  
 
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{{comp table start}}
 
{{comp table start}}
<table class="comptable sortable tc3 tc4 tc6">
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<table class="comptable sortable tc4">
 
{{comp table header|main|5:List of Vulcan-based Processors}}
 
{{comp table header|main|5:List of Vulcan-based Processors}}
 
{{comp table header|main|5:Main processor}}
 
{{comp table header|main|5:Main processor}}
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== See also ==
 
== See also ==
* [http://www.marvell.com/server-processors/thunderx2-arm-processors/index.jsp Marvell ThunderX2 Arm Processors]
 
* [http://www.marvell.com/documents/hrur6mybdvk5uki1w0z7/ Marvell ThunderX2 CN99XX PMU Events (Abridged)]
 
 
* Qualcomm's {{qualcomm|Centriq}}
 
* Qualcomm's {{qualcomm|Centriq}}
 
* Intel's {{intel|Xeon Platinum}}, {{intel|Xeon Gold|Gold}}, and {{intel|Xeon Silver|Silver}}
 
* Intel's {{intel|Xeon Platinum}}, {{intel|Xeon Gold|Gold}}, and {{intel|Xeon Silver|Silver}}

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Facts about "ThunderX2 - Cavium"
designerCavium +
first announcedMay 30, 2016 +
first launchedMay 7, 2018 +
full page namecavium/thunderx2 +
instance ofmicroprocessor family +
instruction set architectureARMv8.1 +
main designerCavium +
manufacturerTSMC +
microarchitectureThunderX2 + and Vulcan +
nameThunderX2 +
process14 nm (0.014 μm, 1.4e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +