From WikiChip
Editing cavium/thunderx2

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 35: Line 35:
  
 
== Models ==
 
== Models ==
=== CN99xx ===
+
=== Vulcan ===
{{see also|cavium/microarchitectures/vulcan|l1=Vulcan microarchitecture}}
+
The first parts of the ThunderX2 family that made it to general availability are based on the {{cavium|Vulcan|l=arch}} microarchitecture. Those parts are different from Cavium's original ThunderX2 design which started sampling in 2016. Originally designed by [[Broadcom]], those parts have much higher performance and a slightly different set of features. All parts have the following features in common.
The first parts of the ThunderX2 family, CN99xx series, that made it to general availability are based on the {{cavium|Vulcan|l=arch}} microarchitecture. Those parts are different from Cavium's original ThunderX2 design which started sampling in 2016. Originally designed by [[Broadcom]], those parts have much higher performance and a slightly different set of features. All parts have the following features in common.
 
  
 
* '''Mem:''' Up to 2 TiB of quad/hexa/octa- channel DDR4 2666 MT/s memory
 
* '''Mem:''' Up to 2 TiB of quad/hexa/octa- channel DDR4 2666 MT/s memory

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)
Facts about "ThunderX2 - Cavium"
designerCavium +
first announcedMay 30, 2016 +
first launchedMay 7, 2018 +
full page namecavium/thunderx2 +
instance ofmicroprocessor family +
instruction set architectureARMv8.1 +
main designerCavium +
manufacturerTSMC +
microarchitectureThunderX2 + and Vulcan +
nameThunderX2 +
process14 nm (0.014 μm, 1.4e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +