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| first announced = May 30, 2016 | | first announced = May 30, 2016 | ||
| first launched = May 7, 2018 | | first launched = May 7, 2018 | ||
− | | isa = ARMv8 | + | | isa = ARMv8 |
| microarch = ThunderX2 | | microarch = ThunderX2 | ||
| microarch 2 = Vulcan | | microarch 2 = Vulcan | ||
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| predecessor = ThunderX | | predecessor = ThunderX | ||
| predecessor link = cavium/thunderx | | predecessor link = cavium/thunderx | ||
− | | successor = | + | | successor = |
− | | successor link = | + | | successor link = |
}} | }} | ||
'''ThunderX2''' is a family of {{arch|64}} [[multi-core]] [[ARM]] server microprocessors introduced by [[Cavium]] in early [[2018]] succeeding the original {{\\|ThunderX}} line. | '''ThunderX2''' is a family of {{arch|64}} [[multi-core]] [[ARM]] server microprocessors introduced by [[Cavium]] in early [[2018]] succeeding the original {{\\|ThunderX}} line. | ||
== Overview == | == Overview == | ||
− | The ThunderX2 was designed to succeed the original {{\\|ThunderX}} family. [[Cavium]] first announced the ThunderX2 back in May 30 2016 with models based on their own {{cavium|thunderx2|second-generation|l=arch}} microarchitecture with models up to 54 cores. Cavium | + | The ThunderX2 was designed to succeed the original {{\\|ThunderX}} family. [[Cavium]] first announced the ThunderX2 back in May 30 2016 with models based on their own {{cavium|thunderx2|second-generation|l=arch}} microarchitecture with models up to 54 cores. Cavium eventually scrapped their own design and in late 2016 they acquired the {{cavium|Vulcan|l=arch}} design from [[Broadcom]] which has designed a server microprocessor but has given up on the project for reasons not well understood. In early 2018, Cavium announced that their ThunderX2 processors (now based on {{cavium|Vulcan|l=arch}}) have reached general availability. |
== Models == | == Models == | ||
− | === | + | === Vulcan === |
− | + | The first parts of the ThunderX2 family that made it to general availability are based on the {{cavium|Vulcan|l=arch}} microarchitecture. Those parts are different from Cavium's original ThunderX2 design which started sampling in 2016. Originally designed by [[Broadcom]], those parts have much higher performance and a slightly different set of features. All parts have the following features in common. | |
− | The first parts of the ThunderX2 family | ||
* '''Mem:''' Up to 2 TiB of quad/hexa/octa- channel DDR4 2666 MT/s memory | * '''Mem:''' Up to 2 TiB of quad/hexa/octa- channel DDR4 2666 MT/s memory | ||
** Up to 4 TiB in dual-socket configuration | ** Up to 4 TiB in dual-socket configuration | ||
− | * '''ISA:''' [[ | + | * '''ISA:''' [[ARMv8]], 128-bit {{arm|SVE}} |
* '''I/O:''' x48, x56 PCIe Gen 3 Lanes | * '''I/O:''' x48, x56 PCIe Gen 3 Lanes | ||
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== See also == | == See also == | ||
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* Qualcomm's {{qualcomm|Centriq}} | * Qualcomm's {{qualcomm|Centriq}} | ||
* Intel's {{intel|Xeon Platinum}}, {{intel|Xeon Gold|Gold}}, and {{intel|Xeon Silver|Silver}} | * Intel's {{intel|Xeon Platinum}}, {{intel|Xeon Gold|Gold}}, and {{intel|Xeon Silver|Silver}} |
Facts about "ThunderX2 - Cavium"
designer | Cavium + |
first announced | May 30, 2016 + |
first launched | May 7, 2018 + |
full page name | cavium/thunderx2 + |
instance of | microprocessor family + |
instruction set architecture | ARMv8.1 + |
main designer | Cavium + |
manufacturer | TSMC + |
microarchitecture | ThunderX2 + and Vulcan + |
name | ThunderX2 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |