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Information for "cavium/octeon plus/cn5860-800bg1521-exp"

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Display titleCN5860-800 EXP - Cavium
Default sort keyCN5860-800 EXP, Cavium
Page length (in bytes)3,662
Page ID12287
Page content languageEnglish (en)
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Page creatorChipIt (talk | contribs)
Date of page creation00:09, 15 December 2016
Latest editorChippyBot (talk | contribs)
Date of latest edit16:13, 13 December 2017
Total number of edits10
Total number of distinct authors2
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Retrieved from "https://en.wikichip.org/wiki/cavium/octeon_plus/cn5860-800bg1521-exp"
Facts about "CN5860-800 EXP - Cavium"
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CN5860-800 EXP - Cavium#package +
base frequency800 MHz (0.8 GHz, 800,000 kHz) +
core count16 +
designerCavium +
familyOCTEON Plus +
first announcedOctober 9, 2006 +
first launchedFebruary 2007 +
full page namecavium/octeon plus/cn5860-800bg1521-exp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description64-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description64-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateFebruary 2007 +
main imageFile:octeon plus chip.png +
manufacturerTSMC +
market segmentNetwork +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN5860-800 EXP +
nameCavium CN5860-800 EXP +
packageFCBGA-1521 +
part numberCN5860-800BG1521-EXP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN58xx +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count16 +
word size64 bit (8 octets, 16 nibbles) +