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Information for "cavium/octeon plus/cn5750-900bg1217-sp"

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Display titleCN5750-900 SP - Cavium
Default sort keyCN5750-900 SP, Cavium
Page length (in bytes)3,665
Page ID12391
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page6
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

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Page creatorChipIt (talk | contribs)
Date of page creation21:43, 28 December 2016
Latest editorChippyBot (talk | contribs)
Date of latest edit16:12, 13 December 2017
Total number of edits6
Total number of distinct authors2
Recent number of edits (within past 90 days)0
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CN5750-900 SP - Cavium#package +
base frequency900 MHz (0.9 GHz, 900,000 kHz) +
core count12 +
designerCavium +
familyOCTEON Plus +
first announcedJune 26, 2007 +
first launchedAugust 2007 +
full page namecavium/octeon plus/cn5750-900bg1217-sp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size0.563 MiB (576 KiB, 589,824 B, 5.493164e-4 GiB) +
l1d$ size0.188 MiB (192 KiB, 196,608 B, 1.831055e-4 GiB) +
l1i$ size0.375 MiB (384 KiB, 393,216 B, 3.662109e-4 GiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateAugust 2007 +
main imageFile:Octeon CN57xx.svg +
manufacturerTSMC +
market segmentStorage +
max cpu count1 +
max memory channels2 +
max pcie lanes8 +
microarchitecturecnMIPS +
model numberCN5750-900 SP +
nameCavium CN5750-900 SP +
packageFCBGA-1217 +
part numberCN5750-900BG1217-SP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN57xx +
supported memory typeDDR2-800 +
technologyCMOS +
thread count12 +
word size64 bit (8 octets, 16 nibbles) +