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CN5750-900 SP - Cavium#package + and CN5750-900 SP - Cavium#io +
base frequency900 MHz (0.9 GHz, 900,000 kHz) +
core count12 +
designerCavium +
familyOCTEON Plus +
first announcedJune 26, 2007 +
first launchedAugust 2007 +
full page namecavium/octeon plus/cn5750-900bg1217-sp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size0.563 MiB (576 KiB, 589,824 B, 5.493164e-4 GiB) +
l1d$ size0.188 MiB (192 KiB, 196,608 B, 1.831055e-4 GiB) +
l1i$ size0.375 MiB (384 KiB, 393,216 B, 3.662109e-4 GiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateAugust 2007 +
main imageFile:Octeon CN57xx.svg +
manufacturerTSMC +
market segmentStorage +
max cpu count1 +
max memory bandwidth11.92 GiB/s (20.741 GB/s, 12,206.08 MiB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
microarchitecturecnMIPS +
model numberCN5750-900 SP +
nameCavium CN5750-900 SP +
packageFCBGA-1217 +
part numberCN5750-900BG1217-SP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN57xx +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count12 +
word size64 bit (8 octets, 16 nibbles) +