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'''CN5750-600 SP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] storage processor (SP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], networking, TCP & [[QoS]] acceleration.
 
'''CN5750-600 SP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] storage processor (SP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], networking, TCP & [[QoS]] acceleration.
 
== Cache ==
 
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
 
{{cache size
 
|l1 cache=576 KiB
 
|l1i cache=384 KiB
 
|l1i break=12x32 KiB
 
|l1d cache=192 KiB
 
|l1d break=12x16 KiB
 
|l2 cache=2 MiB
 
|l2 break=1x2 MiB
 
}}
 
 
== Memory controller ==
 
{{memory controller
 
|type=DDR2-800
 
|ecc=Yes
 
|max mem=
 
|controllers=1
 
|channels=2
 
|width=64 bit
 
|max bandwidth=11.92 GiB/s
 
|bandwidth schan=5.96 GiB/s
 
|bandwidth dchan=11.92 GiB/s
 
}}
 
 
== Expansions ==
 
{{expansions
 
|pcie revision=1.0
 
|pcie lanes=8
 
|pcie config=x4
 
|pcie config 2=x8
 
|uart=yes
 
|gp io=Yes
 
}}
 
 
== Networking ==
 
Interface options:
 
* 8-lanes [[PCIe]] + 8-lanes PCIe
 
* 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
 
* 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
 
{{network
 
|mii opts=Yes
 
|sgmii=yes
 
|sgmii ports=4
 
|xaui=1
 
|xaui ports=1
 
}}
 
 
== Hardware Accelerators ==
 
{{accelerators
 
|compression=Yes
 
|decompression=Yes
 
|tcp=Yes
 
|qos=Yes
 
|raid=Yes
 
|raid5=Yes
 
|raid6=Yes
 
}}
 
 
== Block diagram ==
 
[[File:cn57xx block diagram.png|750px]]
 
 
== Datasheet ==
 
* [[:File:CN57XX PB Rev 1.2.pdf|OCTEON CN57XX Processors Product Brief]]
 

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CN5750-600 SP - Cavium#package + and CN5750-600 SP - Cavium#io +
base frequency600 MHz (0.6 GHz, 600,000 kHz) +
core count12 +
designerCavium +
familyOCTEON Plus +
first announcedJune 26, 2007 +
first launchedAugust 2007 +
full page namecavium/octeon plus/cn5750-600bg1217-sp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size576 KiB (589,824 B, 0.563 MiB) +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateAugust 2007 +
main imageFile:Octeon CN57xx.svg +
manufacturerTSMC +
market segmentStorage +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
microarchitecturecnMIPS +
model numberCN5750-600 SP +
nameCavium CN5750-600 SP +
packageFCBGA-1217 +
part numberCN5750-600BG1217-SP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN57xx +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count12 +
word size64 bit (8 octets, 16 nibbles) +