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CN5734-900 SSP - Cavium#package + and CN5734-900 SSP - Cavium#io +
base frequency900 MHz (0.9 GHz, 900,000 kHz) +
core count6 +
designerCavium +
familyOCTEON Plus +
first announcedJune 26, 2007 +
first launchedAugust 2007 +
full page namecavium/octeon plus/cn5734-900bg1217-ssp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size0.281 MiB (288 KiB, 294,912 B, 2.746582e-4 GiB) +
l1d$ size0.0938 MiB (96 KiB, 98,304 B, 9.155273e-5 GiB) +
l1i$ size0.188 MiB (192 KiB, 196,608 B, 1.831055e-4 GiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateAugust 2007 +
main imageFile:Octeon CN57xx.svg +
manufacturerTSMC +
market segmentStorage +
max cpu count1 +
max memory bandwidth11.92 GiB/s (20.741 GB/s, 12,206.08 MiB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
microarchitecturecnMIPS +
model numberCN5734-900 SSP +
nameCavium CN5734-900 SSP +
packageFCBGA-1217 +
part numberCN5734-900BG1217-SSP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN57xx +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count6 +
word size64 bit (8 octets, 16 nibbles) +