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== Members ==
 
== Members ==
=== CN50xx Series ===
 
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=== CN52xx Series ===
 
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=== CN54xx Series ===
 
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=== CN55xx Series ===
 
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=== CN56xx Series ===
 
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=== CN57xx Series ===
 
=== CN57xx Series ===
 
The CN57xx series come with [[6 cores|6]] to [[12 cores|12]] {{cavium|cnMIPS|l=arch}} cores. CN57xx series is designed for storage devices, incorporating hardware support for [[RAID]] 5 and 6. All models incorporate the following features:
 
The CN57xx series come with [[6 cores|6]] to [[12 cores|12]] {{cavium|cnMIPS|l=arch}} cores. CN57xx series is designed for storage devices, incorporating hardware support for [[RAID]] 5 and 6. All models incorporate the following features:

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Facts about "OCTEON Plus - Cavium"
designerCavium +
first announcedOctober 9, 2006 +
first launchedFebruary 2007 +
full page namecavium/octeon plus +
instance ofsystem on a chip family +
instruction set architectureMIPS64 +
main designerCavium +
manufacturerTSMC +
microarchitecturecnMIPS +
nameCavium OCTEON Plus +
packageFCBGA-1521 +
process90 nm (0.09 μm, 9.0e-5 mm) +
socketBGA-1521 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +