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Information for "cavium/octeon/cn3830-500bg1521-scp"

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Display titleCN3830-500 SCP - Cavium
Default sort keyCN3830-500 SCP, Cavium
Page length (in bytes)3,781
Page ID12121
Page content languageEnglish (en)
Page content modelwikitext
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Number of redirects to this page6
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Page creatorChipIt (talk | contribs)
Date of page creation19:16, 10 December 2016
Latest editorChippyBot (talk | contribs)
Date of latest edit16:11, 13 December 2017
Total number of edits7
Total number of distinct authors2
Recent number of edits (within past 90 days)0
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CN3830-500 SCP - Cavium#package +
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count4 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedSeptember 13, 2004 +
first launchedJune 1, 2005 +
full page namecavium/octeon/cn3830-500bg1521-scp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size0.156 MiB (160 KiB, 163,840 B, 1.525879e-4 GiB) +
l1d$ description64-way set associative +
l1d$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) +
l1i$ description64-way set associative +
l1i$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateJune 1, 2005 +
main imageFile:octeon cn38xx.png +
manufacturerTSMC +
market segmentNetworking +
max cpu count1 +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth11.92 GiB/s (20.741 GB/s, 12,206.08 MiB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3830-500 SCP +
nameCavium CN3830-500 SCP +
packageFCBGA-1521 +
part numberCN3830-500BG1521-SCP +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3800 +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count4 +
word size64 bit (8 octets, 16 nibbles) +