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Difference between revisions of "cavium/octeon/cn3120-550bg868-scp"
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{{cavium title|CN3120-550 SCP}}
 
{{cavium title|CN3120-550 SCP}}
{{mpu
+
{{chip
 
| name                = Cavium CN3120-550 SCP
 
| name                = Cavium CN3120-550 SCP
 
| no image            =  
 
| no image            =  
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| designer            = Cavium
 
| designer            = Cavium
 
| manufacturer        = TSMC
 
| manufacturer        = TSMC
| model number        = CN3120
+
| model number        = CN3120-550 SCP
 
| part number        = CN3120-550BG868-SCP
 
| part number        = CN3120-550BG868-SCP
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Embedded
 
| market              = Embedded
 
| first announced    = January 30, 2006  
 
| first announced    = January 30, 2006  
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| last order          =  
 
| last order          =  
 
| last shipment      =  
 
| last shipment      =  
| release price      =  
+
| release price      = $125.00
  
 
| family              = OCTEON
 
| family              = OCTEON
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| max memory addr    =  
 
| max memory addr    =  
  
| electrical          = Yes
+
 
 
| power              = 7 W
 
| power              = 7 W
 
| v core              =  
 
| v core              =  
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| tambient max        =  
 
| tambient max        =  
  
| packaging          = Yes
+
|package module 1={{packages/cavium/hsbga-868}}
| package 0          = BGA-868
 
| package 0 type      = BGA
 
| package 0 pins      = 868
 
| package 0 pitch    =
 
| package 0 width    =
 
| package 0 length    =
 
| package 0 height    =
 
| socket 0            =
 
| socket 0 type      =
 
 
}}
 
}}
 
The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
 
The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
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}}
 
}}
  
== Features ==
+
== Hardware Accelerators ==
Hardware acceleration units:
+
{{accelerators
* [[Encryption]]
+
|encryption=Yes
** [[DES]], [[3DES]], [[AES]] (up to 256 bit), [[SHA1]], [[SHA-2]] upto [[SHA-512]], [[RSA]], DH
+
|encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
* QoS
+
|tcp=Yes
* TCP Acceleration
+
|qos=Yes
 +
}}
  
 
== Block diagram ==
 
== Block diagram ==

Revision as of 16:11, 13 December 2017

Edit Values
Cavium CN3120-550 SCP
octeon cn31xx.png
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN3120-550 SCP
Part NumberCN3120-550BG868-SCP
MarketEmbedded
IntroductionJanuary 30, 2006 (announced)
May 1, 2006 (launched)
Release Price$125.00
General Specs
FamilyOCTEON
SeriesCN3100
Frequency550 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Core NamecnMIPS
Process130 nm
TechnologyCMOS
Word Size64 bit
Cores2
Threads2
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation7 W
Packaging
PackageHSBGA-868 (BGA)
Ball Count868
InterconnectBGA-868

The CN3120-550 SCP is a 64-bit dual-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$80 KiB
81,920 B
0.0781 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 
L1D$16 KiB
16,384 B
0.0156 MiB
2x8 KiB64-way set associativeWrite-through

L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x128 KiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem4 GiB
Controllers1
Channels1
Width64 bit
Max Bandwidth4.97 GiB/s
5,089.28 MiB/s
5.336 GB/s
5,336.497 MB/s
0.00485 TiB/s
0.00534 TB/s
Bandwidth
Single 4.97 GiB/s

Optional low-latency controller for content-based processing and meta data

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem2 GiB
Controllers1
Channels1
Width16 bit
Max Bandwidth1.24 GiB/s
1,269.76 MiB/s
1.331 GB/s
1,331.44 MB/s
0.00121 TiB/s
0.00133 TB/s
Bandwidth
Single 1.24 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width32 bit
Clock100 MHz
Rate381.5 MiB/s
USB
Revision2.0
Ports1
Rate60 MB/s
Featureshost / PHY
UART
Ports2

GP I/OYes


Networking

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
GMIIYes (Ports: 1)
RGMIIYes (Ports: 3)
TDM/PCMYes

Hardware Accelerators

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
TypesDES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
Networking
TCPYes
QoSYes

Block diagram

octeon cn31xx block diagram.png

Datasheet

Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN3120-550 SCP - Cavium#package +
base frequency550 MHz (0.55 GHz, 550,000 kHz) +
core count2 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedJanuary 30, 2006 +
first launchedMay 1, 2006 +
full page namecavium/octeon/cn3120-550bg868-scp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size80 KiB (81,920 B, 0.0781 MiB) +
l1d$ description64-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldateMay 1, 2006 +
main imageFile:octeon cn31xx.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory bandwidth4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3120-550 SCP +
nameCavium CN3120-550 SCP +
packageHSBGA-868 +
part numberCN3120-550BG868-SCP +
power dissipation7 W (7,000 mW, 0.00939 hp, 0.007 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
release price$ 125.00 (€ 112.50, £ 101.25, ¥ 12,916.25) +
seriesCN3100 +
smp max ways1 +
supported memory typeDDR2-667 +
technologyCMOS +
thread count2 +
word size64 bit (8 octets, 16 nibbles) +