From WikiChip
Difference between revisions of "cavium/octeon/cn3110-550bg868-scp"
< cavium‎ | octeon

Line 8: Line 8:
 
| designer            = Cavium
 
| designer            = Cavium
 
| manufacturer        = TSMC
 
| manufacturer        = TSMC
| model number        = CN3110
+
| model number        = CN3110-550 SCP
 
| part number        = CN3110-550BG868-SCP
 
| part number        = CN3110-550BG868-SCP
 
| part number 1      =  
 
| part number 1      =  

Revision as of 15:59, 9 December 2016

Template:mpu The CN3110-550 SCP is a 64-bit single-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2006. This processor, which incorporates a cnMIPS core, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$40 KiB
40,960 B
0.0391 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB4-way set associative 
L1D$8 KiB
8,192 B
0.00781 MiB
1x8 KiB64-way set associativeWrite-through

L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem4 GiB
Controllers1
Channels1
Width64 bit
Max Bandwidth4.97 GiB/s
5,089.28 MiB/s
5.336 GB/s
5,336.497 MB/s
0.00485 TiB/s
0.00534 TB/s
Bandwidth
Single 4.97 GiB/s

Optional low-latency controller for content-based processing and meta data

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem2 GiB
Controllers1
Channels1
Width16 bit
Max Bandwidth1.24 GiB/s
1,269.76 MiB/s
1.331 GB/s
1,331.44 MB/s
0.00121 TiB/s
0.00133 TB/s
Bandwidth
Single 1.24 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width32 bit
Clock100 MHz
Rate381.5 MiB/s
USB
Revision2.0
Ports1
Rate60 MB/s
Featureshost / PHY
UART
Ports2

GP I/OYes


Networking

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
GMIIYes (Ports: 1)
RGMIIYes (Ports: 3)
TDM/PCMYes

Features

Hardware acceleration units:

Block diagram

octeon cn31xx block diagram.png

Datasheet

has ecc memory supporttrue +
l1$ size40 KiB (40,960 B, 0.0391 MiB) +
l1d$ description64-way set associative +
l1d$ size8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description4-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
max memory bandwidth4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) +
max memory channels1 +
supported memory typeDDR2-667 +