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Difference between revisions of "cavium/octeon/cn3110-550bg868-nsp"
< cavium‎ | octeon

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The '''CN3110-550 NSP''' is a {{arch|64}} [[single-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network services such as [[encryption]], [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Revision as of 02:34, 9 December 2016

Template:mpu The CN3110-550 NSP is a 64-bit single-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network services such as encryption, compression & decompression, RegEx engine, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.