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CN3110-500 NSP - Cavium
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Revision as of 13:42, 9 December 2016 by ChipIt (talk | contribs) (Cache)

Template:mpu The CN3110-500 NSP is a 64-bit single-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 500 MHz. This processor includes a number of hardware accelerators for network services such as encryption, compression & decompression, RegEx engine, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$40 KiB
40,960 B
0.0391 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB4-way set associative 
L1D$8 KiB
8,192 B
0.00781 MiB
1x8 KiB64-way set associativeWrite-through

L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB8-way set associative 
l1$ size40 KiB (40,960 B, 0.0391 MiB) +
l1d$ description64-way set associative +
l1d$ size8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description4-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +