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Difference between revisions of "cavium/octeon/cn3005-400bg350-scp"
< cavium‎ | octeon

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| part number 3      =  
 
| part number 3      =  
 
| market              = Embedded
 
| market              = Embedded
| first announced    = September 13, 2004
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| first announced    = January 30, 2006
| first launched      = June 1, 2005
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| first launched      = May 1, 2006
 
| last order          =  
 
| last order          =  
 
| last shipment      =  
 
| last shipment      =  
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| socket 0 type      =  
 
| socket 0 type      =  
 
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The '''CN3005-400 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 400 MHz and dissipates 3 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration.
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The '''CN3005-400 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in early [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 400 MHz and dissipates 3 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration.

Revision as of 05:41, 8 December 2016

Template:mpu The CN3005-400 SCP is a 64-bit single-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in early 2006. This processor, which incorporates a single cnMIPS core, operates at 400 MHz and dissipates 3 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration.