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Editing cavium/octeon/cn3005-400bg350-scp (section)

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base frequency400 MHz (0.4 GHz, 400,000 kHz) +
core count1 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedJanuary 30, 2006 +
first launchedMay 1, 2006 +
full page namecavium/octeon/cn3005-400bg350-scp +
has ecc memory supportfalse +
has hardware accelerators for cryptographytrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size0.0234 MiB (24 KiB, 24,576 B, 2.288818e-5 GiB) +
l1d$ description64-way set associative +
l1d$ size0.00781 MiB (8 KiB, 8,192 B, 7.629395e-6 GiB) +
l1i$ description2-way set associative +
l1i$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
l2$ description2-way set associative +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
ldateMay 1, 2006 +
main imageFile:cn3005-15.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth0.993 GiB/s (1.728 GB/s, 1,017 MiB/s, 9.69924e-4 TiB/s, 0.00107 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3005-400 SCP +
nameCavium CN3005-400 SCP +
part numberCN3005-400BG350-SCP +
power dissipation3 W (3,000 mW, 0.00402 hp, 0.003 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3000 +
smp max ways1 +
supported memory typeDDR2-533 +
technologyCMOS +
thread count1 +
word size64 bit (8 octets, 16 nibbles) +