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Difference between revisions of "cavium/octeon/cn3005-300bg350-cp"
< cavium‎ | octeon

(Created page with "{{cavium title|CN3005 300 MHz CP}} {{mpu | name = Cavium CN3005-300 CP | no image = cn3005-15.png | image = | image size = |...")
 
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| die width          =  
 
| die width          =  
 
| die length          =  
 
| die length          =  
| word size          =  
+
| word size          = 64 bit
| core count          =  
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| core count          = 1
| thread count        =  
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| thread count        = 1
| max cpus            =  
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| max cpus            = 1
 
| max memory          = 2 GiB
 
| max memory          = 2 GiB
 
| max memory addr    =  
 
| max memory addr    =  

Revision as of 06:24, 8 December 2016

Template:mpu The CN3005-300 CP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2005. This processor, which incorporates a single cnMIPS core, operates at 300 MHz and dissipates 2 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration.