Semiconductor & Computer Engineering
From WikiChip
Information for "cavium/octeon/cn3005-300bg350-cp"
Basic information
| Display title | CN3005-300 CP - Cavium |
| Default sort key | CN3005-300 CP, Cavium |
| Page length (in bytes) | 3,894 |
| Page ID | 11993 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 6 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | ChipIt (talk | contribs) |
| Date of page creation | 06:15, 8 December 2016 |
| Latest editor | ChippyBot (talk | contribs) |
| Date of latest edit | 16:10, 13 December 2017 |
| Total number of edits | 21 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (15) | Templates used on this page:
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Facts about "CN3005-300 CP - Cavium"
| has ecc memory support | true + |
| l1$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
| l1d$ description | 64-way set associative + |
| l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l2$ description | 2-way set associative + |
| l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |
| max memory bandwidth | 0.993 GiB/s (1,017 MiB/s, 1.066 GB/s, 1,066.402 MB/s, 9.698868e-4 TiB/s, 0.00107 TB/s) + |
| max memory channels | 1 + |
| supported memory type | DDR2-533 + |
