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OCTEON - Cavium
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Cavium OCTEON
octeon cn38xx.png
CN38xx
Developer Cavium
Manufacturer TSMC
Type System on chips
Introduction September 13, 2004 (announced)
Architecture MIPS64 R2 network SoCs
ISA MIPS64
µarch cnMIPS
Word size 64 bit
8 octets
16 nibbles
Process 130 nm
0.13 μm
1.3e-4 mm
Technology CMOS
Clock 400 MHz-600 MHz
Package FCBGA-1521
Socket BGA-1521
Succession
→
OCTEON II

OCTEON was a family of 64-bit multi-core MIPS microprocessors designed by Cavium for networking devices.

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon&oldid=30577"
Facts about "OCTEON - Cavium"
RDF feed
designerCavium +
first announcedSeptember 13, 2004 +
full page namecavium/octeon +
instance ofsystem on a chip family +
instruction set architectureMIPS64 +
main designerCavium +
manufacturerTSMC +
microarchitecturecnMIPS +
nameCavium OCTEON +
packageFCBGA-1521 +
process130 nm (0.13 μm, 1.3e-4 mm) +
socketBGA-1521 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +