From WikiChip
Editing cavium/microarchitectures/vulcan
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 163: | Line 163: | ||
== Overview == | == Overview == | ||
[[File:vulcan overview.svg|500px|right]] | [[File:vulcan overview.svg|500px|right]] | ||
− | Scaled up from prior architectures in all vectors (performance, area, and [[TDP]]), Vulcan was designed to be a {{intel|Xeon}}-class [[ARM]]-based server microprocessor. Vulcan features 32 high-performance custom-designed [[ARM]] cores fully compliant with [[ARMv8.1]] along with their accompanying 1 MiB of level 3 cache slice (for a total of 32 MiB of shared [[last level cache]]) | + | Scaled up from prior architectures in all vectors (performance, area, and [[TDP]]), Vulcan was designed to be a {{intel|Xeon}}-class [[ARM]]-based server microprocessor. Vulcan features 32 high-performance custom-designed [[ARM]] cores fully compliant with [[ARMv8.1]] along with their accompanying 1 MiB of level 3 cache slice (for a total of 32 MiB of shared [[last level cache]]). Supporting a large number of cores, are eight [[DDR4]] channels capable of data rates of up to 2,666 MT/s, allowing for 170.7 GB/s of aggregated bandwidth. |
The processor comes with 14 fully-configurable PCIe Gen3 controllers with 56 available lanes. The chip also has 2 USB 3 and 2 SATA 3 ports. | The processor comes with 14 fully-configurable PCIe Gen3 controllers with 56 available lanes. The chip also has 2 USB 3 and 2 SATA 3 ports. |
Facts about "Vulcan - Microarchitectures - Cavium"
codename | Vulcan + |
core count | 16 +, 20 +, 24 +, 28 +, 30 + and 32 + |
designer | Cavium + and Broadcom + |
first launched | 2018 + |
full page name | cavium/microarchitectures/vulcan + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.1 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Vulcan + |
pipeline stages (max) | 15 + |
pipeline stages (min) | 13 + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |