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{{cavium title|Cavium Coherent Processor Interconnect (CCPI)}}{{interconnect arch}}
 
{{cavium title|Cavium Coherent Processor Interconnect (CCPI)}}{{interconnect arch}}
 
'''Cavium Coherent Processor Interconnect''' ('''CCPI'''') is an interconnect architecture designed by [[Cavium]] for their microprocessors.
 
'''Cavium Coherent Processor Interconnect''' ('''CCPI'''') is an interconnect architecture designed by [[Cavium]] for their microprocessors.
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== Overview ==
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CCPI is a [[cache coherent]] interconnect architecture designed by [[Cavium]] for their various microprocessors. CCPI is used to support [[symmetric multiprocessing]] on the {{cavium|ThunderX}} and {{cavium|ThunderX2}} families.
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=== Data Rates ===
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<table class="wikitable">
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<tr><th>&nbsp;</th><th>CCPI</th><th>CCPI2</th></tr>
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<tr><th>Signaling Rate</th><td>10 GT/s</td><td>25 GT/s</td></tr>
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<tr><th>Lanes/Link</th><td>24</td><td>24</td></tr>
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<tr><th>Rate/Link</th><td>30 GB/s<br>240 Gb/s</td><td>75 GB/s<br>600 Gb/s</td></tr>
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</table>
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Revision as of 10:16, 16 December 2018

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Cavium Coherent Processor Interconnect (CCPI') is an interconnect architecture designed by Cavium for their microprocessors.

Overview

CCPI is a cache coherent interconnect architecture designed by Cavium for their various microprocessors. CCPI is used to support symmetric multiprocessing on the ThunderX and ThunderX2 families.

Data Rates

 CCPICCPI2
Signaling Rate10 GT/s25 GT/s
Lanes/Link2424
Rate/Link30 GB/s
240 Gb/s
75 GB/s
600 Gb/s


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