Semiconductor & Computer Engineering
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Difference between revisions of "cavium/ccpi"
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<tr><th>Lanes/Link</th><td>24</td><td>24</td></tr> | <tr><th>Lanes/Link</th><td>24</td><td>24</td></tr> | ||
<tr><th>Rate/Link</th><td>30 GB/s<br>240 Gb/s</td><td>75 GB/s<br>600 Gb/s</td></tr> | <tr><th>Rate/Link</th><td>30 GB/s<br>240 Gb/s</td><td>75 GB/s<br>600 Gb/s</td></tr> | ||
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</table> | </table> | ||
| − | + | == See also == | |
| − | + | * {{cavium|ThunderX}} | |
| − | {{ | + | * {{cavium|ThunderX2}} |
Latest revision as of 00:56, 22 June 2019
| Interconnect Architectures | |
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| General | |
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Cavium Coherent Processor Interconnect (CCPI') is an interconnect architecture designed by Cavium for their microprocessors.
Overview[edit]
CCPI is a cache coherent interconnect architecture designed by Cavium for their various microprocessors. CCPI is used to support symmetric multiprocessing on the ThunderX and ThunderX2 families.
Data Rates[edit]
| CCPI | CCPI2 | |
|---|---|---|
| Signaling Rate | 10 GT/s | 25 GT/s |
| Lanes/Link | 24 | 24 |
| Rate/Link | 30 GB/s 240 Gb/s | 75 GB/s 600 Gb/s |
