From WikiChip
Difference between revisions of "bitmain/sophon/bm1880"
< bitmain‎ | sophon

(BM1880)
 
 
(2 intermediate revisions by the same user not shown)
Line 11: Line 11:
 
|first launched=October 17, 2018
 
|first launched=October 17, 2018
 
|family=Sophon
 
|family=Sophon
 +
|isa=RV32I
 +
|isa family=RISC-V
 +
|isa 2=ARMv8
 +
|isa 2 family=ARM
 +
|microarch=Cortex-A53
 +
|microarch 2=RISC-V
 +
|core name=Cortex-A53
 +
|core name 2=RISC-V
 
|technology=CMOS
 
|technology=CMOS
 +
|max memory=4 GiB
 +
|v core=0.9 V
 +
|v io=1.8 V
 +
|v io 2=3.3 V
 +
|tdp typical=2.5 W
 
}}
 
}}
 
'''Sophon BM1880''' is a [[neural processor]] designed by [[Bitmain]] launched in [[2018]] for edge applications. This chip is designed primarily for edge inference acceleration and has a peak performance of [[peak integer ops (8-bit)::2 TOPS]] (INT8) and a typical power consumption of 2.5 W.
 
'''Sophon BM1880''' is a [[neural processor]] designed by [[Bitmain]] launched in [[2018]] for edge applications. This chip is designed primarily for edge inference acceleration and has a peak performance of [[peak integer ops (8-bit)::2 TOPS]] (INT8) and a typical power consumption of 2.5 W.
 +
 +
== Overview ==
 +
The BM1880 is a [[neural processor]] designed for edge inference at low power consumption. The chip integrates a single-core [[RISC-V]] MCU subsystem operating at 1 GHz along with a dual-core {{armh|Cortex-A53|l=arch}} application processor operating at 1.5 GHz along with a TPU subsystem by BitMain capable of up to 2 teraOPS (8-bit integer). The chip also includes a capable video subsystem for video and image processing from a camera directly on-chip.
 +
 +
 +
:[[File:bm1880 block diagram.png|thumb|left|600px|Block Diagram]]
 +
{{clear}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-3200
 +
|ecc=No
 +
|max mem=4 GiB
 +
|controllers=1
 +
|channels=2
 +
|width=32 bit
 +
|max bandwidth=11.92 GiB/s
 +
|bandwidth schan=11.92 GiB/s
 +
}}
 +
 +
== Video Subsystem ==
 +
* H.264 Video decoder
 +
* MJPEG encoder/decoder
 +
* Video Post Processor
 +
* 1080P@60fps or 2 channel 1080p@30fps
 +
 +
== Expansions ==
 +
* One USB 3.0/USB2.0 host/device
 +
* Two Integrated GMAC for RGMII/RMII
 +
* 5xI2C / 16x PWM / 4x UART / Multi GPIO
 +
 +
== Documents ==
 +
* [[:File:BM1880 PB V0.07.pdf|Product Brief]]

Latest revision as of 11:19, 25 December 2018

Edit Values
Sophon BM1880
General Info
DesignerBitmain
ManufacturerTSMC
Model NumberBM1880
MarketEdge Compute
IntroductionOctober 17, 2018 (announced)
October 17, 2018 (launched)
General Specs
FamilySophon
Microarchitecture
ISARV32I (RISC-V), ARMv8 (ARM)
MicroarchitectureCortex-A53, RISC-V
Core NameCortex-A53, RISC-V
TechnologyCMOS
Max Memory4 GiB
Electrical
Vcore0.9 V
VI/O1.8 V, 3.3 V
TDP (Typical)2.5 W
Sophon BM1880 is a neural processor designed by Bitmain launched in 2018 for edge applications. This chip is designed primarily for edge inference acceleration and has a peak performance of 2 TOPS
2,000,000,000,000 OPS
2,000,000,000 KOPS
2,000,000 MOPS
2,000 GOPS
0.002 POPS
(INT8) and a typical power consumption of 2.5 W.

Overview[edit]

The BM1880 is a neural processor designed for edge inference at low power consumption. The chip integrates a single-core RISC-V MCU subsystem operating at 1 GHz along with a dual-core Cortex-A53 application processor operating at 1.5 GHz along with a TPU subsystem by BitMain capable of up to 2 teraOPS (8-bit integer). The chip also includes a capable video subsystem for video and image processing from a camera directly on-chip.


Block Diagram

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-3200
Supports ECCNo
Max Mem4 GiB
Controllers1
Channels2
Width32 bit
Max Bandwidth11.92 GiB/s
20.741 GB/s
12,206.08 MiB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Video Subsystem[edit]

  • H.264 Video decoder
  • MJPEG encoder/decoder
  • Video Post Processor
  • 1080P@60fps or 2 channel 1080p@30fps

Expansions[edit]

  • One USB 3.0/USB2.0 host/device
  • Two Integrated GMAC for RGMII/RMII
  • 5xI2C / 16x PWM / 4x UART / Multi GPIO

Documents[edit]

designerBitmain +
familySophon +
first announcedOctober 17, 2018 +
first launchedOctober 17, 2018 +
full page namebitmain/sophon/bm1880 +
instance ofmicroprocessor +
ldate3000 +
manufacturerTSMC +
market segmentEdge Compute +
model numberBM1880 +
nameSophon BM1880 +
peak integer ops (8-bit)2,000,000,000,000 OPS (2,000,000,000 KOPS, 2,000,000 MOPS, 2,000 GOPS, 2 TOPS, 0.002 POPS, 2.0e-6 EOPS, 2.0e-9 ZOPS) +
technologyCMOS +