From WikiChip
Neoverse N2 - Microarchitectures - ARM
< arm holdings
Revision as of 00:04, 26 April 2021 by David (talk | contribs)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)

Edit Values
Zeus µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
Introduction2020
Process7 nm
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Succession

Neoverse N2 (codename Perseus) is the successor to Ares, a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

History[edit]

Arm's server roadmap.

Zeus was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.

Release Dates[edit]

Zeus is expected to show up in products around 2020.

Process Technology[edit]

Zeus specifically designed takes advantage of the power and area advantages of the 7nm+ process.

Architecture[edit]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Ares[edit]

This list is incomplete; you can help by expanding it.

Bibliography[edit]

  • Drew Henry keynote, TechCon 2018 keynote.
codenameZeus +
designerARM Holdings +
first launched2020 +
full page namearm holdings/microarchitectures/neoverse n2 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameZeus +
process7 nm (0.007 μm, 7.0e-6 mm) +