Semiconductor & Computer Engineering
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Difference between revisions of "arm holdings/microarchitectures/cortex-a710"
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| + | == Architecture == | ||
| + | === New instructions === | ||
| + | * <code>MatMul</code> - New matrix instructions | ||
Revision as of 20:40, 27 October 2019
| Edit Values | |
| Matterhorn µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | 2021 |
| Process | 7 nm, 5 nm |
| Core Configs | 1, 2, 4 |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Succession | |
Matterhorn is the successor to Hercules, a low-power high-performance synthesizable ARM microarchitecture designed by ARM for the mobile market.
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Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Architecture
New instructions
-
MatMul- New matrix instructions
Facts about "Cortex-A710 - Microarchitectures - ARM"
| codename | Matterhorn + |
| core count | 1 +, 2 + and 4 + |
| designer | ARM Holdings + |
| first launched | 2021 + |
| full page name | arm holdings/microarchitectures/cortex-a710 + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Matterhorn + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |
