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Information for "arm holdings/microarchitectures/cortex-m55"

Basic information

Display titleCortex-M55 - Microarchitectures - ARM
Default sort keyCortex-M55, ARM Holdings
Page length (in bytes)12,725
Page ID35906
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page0
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

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Edit history

Page creatorDavid (talk | contribs)
Date of page creation23:54, 15 February 2020
Latest editor99.95.168.248 (talk)
Date of latest edit09:51, 12 January 2021
Total number of edits18
Total number of distinct authors3
Recent number of edits (within past 90 days)1
Recent number of distinct authors1

Page properties

Transcluded templates (18)

Templates used on this page:

codenameCortex-M55 +
core count1 +, 2 + and 4 +
designerARM Holdings +
first launchedFebruary 10, 2020 +
full page namearm holdings/microarchitectures/cortex-m55 +
instance ofmicroarchitecture +
instruction set architectureARMv8.1-M +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-M55 +
pipeline stages (max)5 +
pipeline stages (min)4 +
process55 nm (0.055 μm, 5.5e-5 mm) +, 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) +