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==== TCM subsystem ====
 
==== TCM subsystem ====
The TCM subsystem is somewhat similar to the one found in the {{\\|Cortex-M7}} but comes with a few noticeable differences. The TCM consists of an instruction TCM (I-TCM) and a data TCM (D-TCM). As with the {{\\|Cortex-M7|M7}}, the purpose of the TCM subsystem is to provide deterministic latencies for real-time applications. The instruction TCM is optional and configurable from 0 to 16 MiB with optional ECC support. It is 32-bit wide, allowing up to 4 bytes per cycle to be transferred from the I-TCM to either the [[instruction fetch]] or the [[instruction memory]]. The D-TCM is also optional and is configurable from 0 to 16 MiB in capacity with optional ECC support. Whereas the {{\\|Cortex-M7}} featured two 32-bit data TCM interfaces, the M55 features four 32-bit data TCM interfaces which are split equally using address bits[3:2]. The data TCM interfaces collectively have an aggregated bandwidth of 128-bit per cycle, however since the Helium vector extension features an interface data path of 64-bit, software execution can only generate 64-bit data transfers per cycle. The rest of the bandwidth can be used for other purposes such as data memory access operations, transferring data from and to the TCM simultaneously while the data is read by the core execution. Accesses to TCM memory banks are prioritized for software execution, therefore an attempt by the DMA controller will be stalled while the software is reading from the same TCM bank.
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The TCM subsystem is somewhat similar to the one found in the {{\\|Cortex-M7}} but comes with a few noticeable differences. The TCM consists of an instruction TCM (I-TCM) and a data TCM (D-TCM). As with the {{\\|Cortex-M7|M7}}, the purpose of the TCM subsystem is to provide deterministic latencies for real-time applications. The instruction TCM is optional and configurable from 0 to 16 MiB with optional ECC support. It is 32-bit wide, allowing up to 4 bytes per cycle to be transferred from the I-TCM to either the [[instruction fetch]] or the [[instruction memory]]. The D-TCM is also optional and is configurable from 0 to 16 MiB in capacity with optional ECC support. Whereas the {{\\|Cortex-M7}} featured two 32-bit data TCM interfaces, the M55 features four 32-bit data TCM interfaces which are split equally using address bits[3:2]. The data TCM interfaces collectively have an aggregated bandwidth of 128-bit per cycle, however since the Helium vector extension features an interface data path of 64-bit, software execution can only generate 64-bit data transfers per cycle. The rest of the bandwidth can be used for other purposes such as data memory access operations, transferring data from and to the TCM simultaneously while the data is read by the core execution. Accesses to TCM memory banks are prioritized for software execution, therefore an attempt by the DMA controller will be stalled while the software is reading form the same TCM bank.
  
  

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codenameCortex-M55 +
core count1 +, 2 + and 4 +
designerARM Holdings +
first launchedFebruary 10, 2020 +
full page namearm holdings/microarchitectures/cortex-m55 +
instance ofmicroarchitecture +
instruction set architectureARMv8.1-M +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-M55 +
pipeline stages (max)5 +
pipeline stages (min)4 +
process55 nm (0.055 μm, 5.5e-5 mm) +, 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) +