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{{armh title|Cortex-A75|arch}}
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{{microarchitecture
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|atype=CPU
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|name=Cortex-A75
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|designer=ARM Holdings
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|manufacturer=TSMC
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|introduction=May 29, 2017
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|process=16 nm
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|process 2=14 nm
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|process 3=10 nm
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|process 4=7 nm
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|cores=1
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|cores 2=2
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|oooe=Yes
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|speculative=Yes
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|renaming=Yes
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|stages min=11
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|stages max=13
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|decode=3-way
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|isa=ARMv8.2
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|feature=Hardware virtualization
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|extension=FPU
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|extension 2=NEON
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|l1i=8-64 KiB
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|l1i per=core
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|l1i desc=4-way set associative
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|l1d=8-64 KiB
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|l1d per=core
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|l1d desc=4-way set associative
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|l2=64-256-512 KiB
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|l2 per=core
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|l3=0-4 MiB
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|l3 per=Cluster
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|predecessor=Cortex-A73
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|predecessor link=arm_holdings/microarchitectures/cortex-a73
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|successor=Cortex-A76
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|successor link=arm_holdings/microarchitectures/cortex-a76
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}}
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'''Cortex-A75''' (codename '''Prometheus''') is the successor to the {{armh|Cortex-A73|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A75, which implemented the {{arm|ARMv8.2}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A55}}) in a {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance.
  
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== Compiler support ==
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{| class="wikitable"
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|-
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! Compiler !! Arch-Specific || Arch-Favorable
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|-
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| [[Arm Compiler]] || <code>-mcpu=cortex-a75</code> || <code>-mtune=cortex-a75</code>
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|-
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| [[GCC]] || <code>-mcpu=cortex-a75</code> || <code>-mtune=cortex-a75</code>
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|-
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| [[LLVM]] || <code>-mcpu=cortex-a75</code> || <code>-mtune=cortex-a75</code>
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|}
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If the Cortex-A75 is coupled with the {{\\|Cortex-A55}} in a [[big.LITTLE]] system, GCC also supports the following option:
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{| class="wikitable"
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|-
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! Compiler !! Tune
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|-
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| [[GCC]] || <code>-mtune=cortex-a75.cortex-a55</code>
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|}
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== Architecture ==
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=== Key changes from {{\\|Cortex-A73}} ===
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{{empty section}}
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=== Block Diagram ===
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{{empty section}}
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=== Memory Hierarchy ===
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{{empty section}}

Latest revision as of 23:03, 23 March 2020

Edit Values
Cortex-A75 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionMay 29, 2017
Process16 nm, 14 nm, 10 nm, 7 nm
Core Configs1, 2
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages11-13
Decode3-way
Instructions
ISAARMv8.2
ExtensionsFPU, NEON
Cache
L1I Cache8-64 KiB/core
4-way set associative
L1D Cache8-64 KiB/core
4-way set associative
L2 Cache64-256-512 KiB/core
L3 Cache0-4 MiB/Cluster
Succession

Cortex-A75 (codename Prometheus) is the successor to the Cortex-A73, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A75, which implemented the ARMv8.2 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A55) in a DynamIQ big.LITTLE configuration to achieve better energy/performance.

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
Arm Compiler -mcpu=cortex-a75 -mtune=cortex-a75
GCC -mcpu=cortex-a75 -mtune=cortex-a75
LLVM -mcpu=cortex-a75 -mtune=cortex-a75

If the Cortex-A75 is coupled with the Cortex-A55 in a big.LITTLE system, GCC also supports the following option:

Compiler Tune
GCC -mtune=cortex-a75.cortex-a55

Architecture[edit]

Key changes from Cortex-A73[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Block Diagram[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.
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Facts about "Cortex-A75 - Microarchitectures - ARM"
RDF feed
codenameCortex-A75 +
core count1 + and 2 +
designerARM Holdings +
first launchedMay 29, 2017 +
full page namearm holdings/microarchitectures/cortex-a75 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A75 +
pipeline stages (max)13 +
pipeline stages (min)11 +
process16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) +