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Difference between revisions of "arm holdings/microarchitectures/cortex-a72"
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If the Cortex-A72 is coupled with the {{\\|Cortex-A53}} or the {{\\|Cortex-A35}} in a [[big.LITTLE]] system, GCC also supports the following option:
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If the Cortex-A72 is coupled with the {{\\|Cortex-A53}} or the {{\\|Cortex-A35}} in a [[big.LITTLE]] system, GCC also supports the following options:
  
 
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=== Block Diagram ===
 
=== Block Diagram ===
{{empty section}}
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[https://techreport.com/r.x/cortex-a72/core-block-simplified.gif Cortex-A72 simplified core block]
 
=== Memory Hierarchy ===
 
=== Memory Hierarchy ===
{{empty section}}
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[https://www.cnx-software.com/wp-content/uploads/2015/02/Cortex-A72.jpg Cortex-A72 Memory Hierarchy]
 
 
 
== Die ==
 
== Die ==
 
=== MediaTek [[Helio X20]] ===
 
=== MediaTek [[Helio X20]] ===

Latest revision as of 16:55, 12 October 2019

Edit Values
Cortex-A72 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionApril 23, 2015
Instructions
ISAARMv8
Succession

Cortex-A72 (codename Maya) is the successor to the Cortex-A57, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A72, which implemented the ARMv8 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A53) in a big.LITTLE configuration to achieve better energy/performance.

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
Arm Compiler -mcpu=cortex-a72 -mtune=cortex-a72
GCC -mcpu=cortex-a72 -mtune=cortex-a72
LLVM -mcpu=cortex-a72 -mtune=cortex-a72

If the Cortex-A72 is coupled with the Cortex-A53 or the Cortex-A35 in a big.LITTLE system, GCC also supports the following options:

Compiler Tune
GCC -mtune=cortex-a72.cortex-a53
-mtune=cortex-a72.cortex-a35

Architecture[edit]

Key changes from Cortex-A57[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Block Diagram[edit]

Cortex-A72 simplified core block

Memory Hierarchy[edit]

Cortex-A72 Memory Hierarchy

Die[edit]

MediaTek Helio X20[edit]

  • TSMC 20 nm process
  • 100 mm² die size
  • Quad-core ULP Cortex-A53
    • ~21.81 mm² per cluster
      • ~4.23 mm² per core
  • Quad-core efficient Cortex-A53
    • ~29.73 mm² per cluster
      • ~5.41 mm² per core
  • Dual-core High-performance Cortex-A72 + 1 MiB L2
    • ~27.36 mm² per cluster
      • ~ 9.60 mm² per core
      • ~ 7.50 mm² for 1 MiB L2


mt6797 die.png

Bibliography[edit]

  • Mair, Hugh T., et al. "4.3 A 20nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.
codenameCortex-A72 +
designerARM Holdings +
first launchedApril 23, 2015 +
full page namearm holdings/microarchitectures/cortex-a72 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A72 +