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Cortex-A55 - Microarchitectures - ARM
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Cortex-A55 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC, Samsung, GlobalFoundries, SMIC
IntroductionMay 29, 2017
Process20 nm, 16 nm, 14 nm, 10 nm
Core Configs1, 2, 3, 4
Pipeline
TypeIn-order
OoOENo
SpeculativeNo
Reg RenamingNo
Stages8
Decode2-way
Instructions
ISAARMv8
ExtensionsFPU, NEON, TrustZone
Cache
L1I Cache8-64 KiB/core
2-way set associative
L1D Cache8-64 KiB/core
4-way set associative
L2 Cache64-256 KiB/core
L3 Cache0-4 MiB/Cluster
Succession
Cortex-A55
codenameCortex-A55 +
core count1 +, 2 +, 3 + and 4 +
designerARM Holdings +
first launchedMay 29, 2017 +
full page namearm holdings/microarchitectures/cortex-a55 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +, Samsung +, GlobalFoundries + and SMIC +
microarchitecture typeCPU +
nameCortex-A55 +
pipeline stages8 +
process20 nm (0.02 μm, 2.0e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) +