Editing arm holdings/microarchitectures/cortex-a55

{{armh title|Cortex-A55|arch}}
{{microarchitecture
|atype=CPU
|name=Cortex-A55
|designer=ARM Holdings
|manufacturer=TSMC
|manufacturer 2=Samsung
|manufacturer 3=GlobalFoundries
|manufacturer 4=SMIC
|introduction=May 29, 2017
|process=16 nm
|process 2=14 nm
|process 3=10 nm
|process 4=7 nm
|process 5=12 nm
|cores=1
|cores 2=2
|cores 3=3
|cores 4=4
|cores 9=8
|type=In-order
|oooe=No
|speculative=Yes
|renaming=Yes
|stages=8
|decode=2-way
|isa=ARMv8.2
|feature=Hardware virtualization
|extension=FPU
|extension 2=NEON
|extension 3=TrustZone
|l1i=8-64 KiB
|l1i per=core
|l1i desc=4-way set associative
|l1d=8-64 KiB
|l1d per=core
|l1d desc=4-way set associative
|l2=64-256 KiB
|l2 per=core
|l2 desc=4-way set associative
|l3=0-4 MiB
|l3 per=Cluster
|predecessor=Cortex-A53
|predecessor link=arm_holdings/microarchitectures/cortex-a53
|successor=Cortex-A510
|successor link=arm_holdings/microarchitectures/cortex-a510
}}
'''Cortex-A55''' (codename '''Ananke''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A53|l=arch}}. The Cortex-A55, which implemented the {{arm|ARMv8.2}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A55 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A75|l=arch}}) in {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance.

Note that this microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.

== Process Technology ==
The Cortex-A55 was primarily designed to make use of [[TSMC]]'s [[16 nm process]] with a [[7 nm]] optimized version set for the end of 2017 or early 2018.

== Architecture ==
{{empty section}}

== Licensees ==
Arm named the following companies as licensees.

{{collist
|count = 3
|
* [[AMD]]
* [[Broadcom]]
* [[HiSilicon]]
* [[STMicroelectronics]]
* [[Samsung]]
* [[MediaTek]]
* [[Huawei]]
* [[Unisoc]]
* [[Amlogic]]
}}

== Die ==
{{empty section}}

== All Cortex-A55 Chips ==
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           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
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{{comp table start}}
<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="25">List of all Cortex-A55 Chips</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th></tr>
{{comp table header 1|cols=Launched, Designer, Family, Core, C, T, L2$, L3$, Frequency, Max Mem, Designer, Name, Frequency}}
{{#ask: [[Category:all microprocessor models]] [[microarchitecture::Cortex-A55]]
 |?full page name
 |?model number
 |?first launched
 |?designer
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?max memory#GiB
 |?integrated gpu designer
 |?integrated gpu
 |?integrated gpu base frequency
 |format=template
 |template=proc table 3
 |searchlabel=
 |sort=microprocessor family, model number
 |order=asc,asc
 |userparam=15
 |mainlabel=-
 |limit=100
 |valuesep=,
}}
{{comp table count|ask=[[Category:all microprocessor models]] [[microarchitecture::Cortex-A55]]}}
</table>
{{comp table end}}
@@ Line 54: / Line 54: @@
 == Architecture ==
-The Cortex-A55 is an improved version of the A53 which introduces a number of performance enhancements as well as designed to be implemented based on [[ARM Holding|ARM]]'s {{armh|DynamIQ big.LITTLE}} design.
+{{empty section}}
-=== Key changes from {{\\|Cortex-A53}} ===
-* Higher performance (ARM claims: up to 2x mem perf, up to 15% less power from A53)
-* Implements [[ARMv8.2]] (from ARMv8.0)
-* Designed as a cluster of [[single-core|1]] to [[8 cores|8]] cores
-** Adds DynamIQ Shared Unit (DSU)
-* Branch predictor was re-written
-* Memory subsystem
-** L2
-*** L2 cache is now private to each core (from shared between all cores)
-*** Latency was cut by half
-*** Now runs at the same frequency as the core
-*** Configurable size from 64 KiB to 256 KiB
-** L3
-*** A new L3 cache was introduced
-*** Shared by all cores
-*** Configurable size: 0 MiB - 4 MiB
-* {{arm|NEON}} is improved
-** New instructions
-** Up to 16x 8-bit [[integer]] operations per cycle
-** Up to 8x 16-bit [[floating point]] per cycle
 == Licensees ==
codename	Cortex-A55 +
core count	1 +, 2 +, 3 + and 4 +
designer	ARM Holdings +
first launched	May 29, 2017 +
full page name	arm holdings/microarchitectures/cortex-a55 +
instance of	microarchitecture +
instruction set architecture	ARMv8.2 +
manufacturer	TSMC +, Samsung +, GlobalFoundries + and SMIC +
microarchitecture type	CPU +
name	Cortex-A55 +
pipeline stages	8 +
process	16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) +