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| − | {{armh title|Cortex-A53|arch}}
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| − | {{microarchitecture
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| − | |atype=CPU
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| − | |name=Cortex-A53
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| − | |designer=ARM Holdings
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| − | |manufacturer=TSMC
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| − | |manufacturer 2=Samsung
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| − | |manufacturer 3=GlobalFoundries
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| − | |manufacturer 4=SMIC
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| − | |introduction=October 30, 2012
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| − | |process=40 nm
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| − | |process 2=28 nm
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| − | |process 3=20 nm
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| − | |process 4=16 nm
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| − | |process 5=14 nm
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| − | |process 6=10 nm
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| − | |cores=1
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| − | |cores 2=2
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| − | |cores 3=3
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| − | |cores 4=4
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| − | |type=In-order
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| − | |oooe=No
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| − | |speculative=Yes
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| − | |renaming=No
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| − | |stages=8
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| − | |decode=2-way
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| − | |isa=ARMv8
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| − | |feature=Hardware virtualization
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| − | |extension=FPU
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| − | |extension 2=NEON
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| − | |extension 3=TrustZone
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| − | |l1i=8-64 KiB
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| − | |l1i per=core
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| − | |l1i desc=2-way set associative
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| − | |l1d=8-64 KiB
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| − | |l1d per=core
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| − | |l1d desc=4-way set associative
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| − | |l2=128 KiB - 2 MiB
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| − | |l2 per=cluster
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| − | |l2 desc=16-way set associative
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| − | |predecessor=Cortex-A7
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| − | |predecessor link=arm_holdings/microarchitectures/cortex-a7
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| − | |successor=Cortex-A55
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| − | |successor link=arm_holdings/microarchitectures/cortex-a55
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| − | |pipeline=Yes
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| − | |issues=2
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| − | |core names=<!-- Yes if specify -->
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| − | }}
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| − | '''Cortex-A53''' (formerly '''Apollo''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A7|l=arch}}. The Cortex-A53, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}} or {{armh|Cortex-A72|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance.
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| − | Note that this microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
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| − |
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| − | == Process Technology ==
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| − | {{empty section}}
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| − |
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| − | == Compiler support ==
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| − | {| class="wikitable"
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| − | |-
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| − | ! Compiler !! Arch-Specific || Arch-Favorable || Arch-Target
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| − | |-
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| − | | [[GCC]] || <code>-march=armv8-a</code> || <code>-mtune=cortex-a53</code> || <code>-mcpu=cortex-a53</code>
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| − | |-
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| − | | [[LLVM]] || <code>-march=armv8-a</code> || <code>-mtune=cortex-a53</code> || <code>-mcpu=cortex-a53</code>
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| − | |}
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| − |
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| − | Note that for big.LITTLE systems it's possible to specify more specific performance tunes:
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| − |
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| − | * <code>-mtune=cortex-a57.cortex-a53</code>
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| − | * <code>-mtune=cortex-a72.cortex-a53</code>
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| − | * <code>-mtune=cortex-a73.cortex-a53</code>
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| − |
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| − |
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| − |
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| − | == Architecture ==
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| − | === Key changes from {{\\|Cortex-A7}} ===
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| − | {{empty section}}
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| − | === Block Diagram ===
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| − | {{empty section}}
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| − | === Memory Hierarchy ===
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| − | {{empty section}}
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| − |
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| − | == Licensees ==
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| − | Arm named the following companies as licensees.
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| − |
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| − | {{collist
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| − | |count = 3
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| − | |
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| − | * [[AMD]]
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| − | * [[Broadcom]]
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| − | * [[Samsung]]
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| − | * [[Altera]]
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| − | * [[STmicroelectronics]]
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| − | * [[MediaTek]]
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| − | * [[Qualcomm]]
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| − | * [[Xilinx]]
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| − | }}
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| − |
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| − | == Die ==
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| − | === 20 nm ===
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| − | ==== Samsung [[Exynos 5433]] ====
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| − | * Samsung [[20 nm process]]
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| − | * 113 mm² die size
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| − | * Mali-T760 (6 EU)
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| − | * Quad-core Cortex-A53 ([[small cores]])
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| − | ** 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
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| − | ** 4.4 mm² per cluster
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| − | *** ~1 mm² per core
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| − | *** ~0.55 mm² for 256 KiB L2 cache
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| − | * Quad-core {{\\|Cortex-A57}} ([[big cores]])
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| − | ** 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
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| − | ** 15.85 mm² per cluster
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| − | *** ~3 mm² per core
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| − | *** ~3.87 mm² for 2 MiB L2 cache
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| − |
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| − |
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| − | :[[File:exynos 5433 die.png|600px]]
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| − |
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| − | ==== MediaTek [[Helio X20]] ====
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| − |
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| − | * TSMC [[20 nm process]]
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| − | * 100 mm² die size
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| − | * Quad-core ULP Cortex-A53
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| − | ** ~21.81 mm² per cluster
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| − | *** ~4.23 mm² per core
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| − | * Quad-core efficient Cortex-A53
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| − | ** ~29.73 mm² per cluster
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| − | *** ~5.41 mm² per core
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| − | * Dual-core High-performance {{\\|Cortex-A72}} + 1 MiB L2
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| − | ** ~27.36 mm² per cluster
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| − | *** ~ 9.60 mm² per core
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| − | *** ~ 7.50 mm² for 1 MiB L2
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| − |
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| − |
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| − | :[[File:mt6797 die.png|600px]]
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| − |
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| − | === 16 nm ===
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| − | ==== Renesas [[R-Car H3]] ====
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| − | * TSMC [[16 nm process]]
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| − | * 12.94 mm × 8.61 mm
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| − | * 111.36 mm² die size
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| − | * Quad-core Cortex-A53
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| − | ** ~3.27 mm² cluster
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| − | ** ~0.60 mm² core
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| − | ** ~0.7`mm² L2 cache
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| − | * Quad-core {{\\|Cortex-A57}}
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| − | ** ~10.21 mm² cluster
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| − | ** ~1.66 mm² core
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| − | ** ~3.28 mm² L2 cache
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| − | * {{\\|Cortex-R7}} (dual-core [[lock-step]])
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| − | ** ~1.04 mm² cluster
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| − | * GX6650 GPU
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| − | ** ~28.12 mm²
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| − |
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| − |
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| − | : [[File:r-car h3 die shot.png|650px]]
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| − |
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| − | == All Cortex-A53 Chips ==
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − |
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| − | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
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| − | <tr class="comptable-header"><th> </th><th colspan="25">List of all Cortex-A53 Chips</th></tr>
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| − | <tr class="comptable-header"><th> </th><th colspan="10">Main processor</th><th colspan="3">IGP</th></tr>
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| − | {{comp table header 1|cols=Launched, Designer, Family, Process, Core, C, T, L2$, L3$, Frequency, Max Mem, Designer, Name, Frequency}}
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| − | {{#ask: [[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]]
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| − | |?full page name
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| − | |?model number
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| − | |?first launched
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| − | |?designer
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| − | |?microprocessor family
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| − | |?process
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| − | |?core name
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| − | |?core count
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| − | |?thread count
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| − | |?l2$ size
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| − | |?l3$ size
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| − | |?base frequency#GHz
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| − | |?max memory#GiB
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| − | |?integrated gpu designer
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| − | |?integrated gpu
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| − | |?integrated gpu base frequency
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| − | |format=template
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| − | |template=proc table 3
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| − | |searchlabel=
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| − | |sort=microprocessor family, model number
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| − | |order=asc,asc
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| − | |userparam=15
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| − | |mainlabel=-
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| − | |limit=100
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| − | |valuesep=,
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| − | }}
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| − | {{comp table count|ask=[[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]]}}
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| − | </table>
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| − | {{comp table end}}
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| − |
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| − | == Bibliography ==
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| − | * Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015
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| − | * Mair, Hugh T., et al. "4.3 A 20nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.
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