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Difference between revisions of "arm holdings/microarchitectures/cortex-a15"
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(Key changes from {{\\|Cortex-A9}})
(Key changes from {{\\|Cortex-A9}})
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* Memory subsystem
 
* Memory subsystem
 
** Level 1 instruction cache switched to [[PIPT]] (from [[VIPT]])  
 
** Level 1 instruction cache switched to [[PIPT]] (from [[VIPT]])  
 +
** Level 1 [[instruction cache]] reduced to 2-way set associative (down from 4-way)
 +
** Level 1 [[data cache]] reduced to 2-way set associative (down from 4-way)
 
** Added {{arm|LPAE}} support
 
** Added {{arm|LPAE}} support
  

Revision as of 01:00, 31 December 2018

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Cortex-A15 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionSeptember 8, 2010
Succession

Cortex-A15 (codename Eagle) is the successor to the Cortex-A9, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The A15 is the first microarchitecture specifically designed for high-performance, whereas the Cortex-A12 (and the A17), also the successor to the Cortex-A9, target high-efficiency.

Architecture

Key changes from Cortex-A9

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Block Diagram

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Memory Hierarchy

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Licensees

Arm named the following companies as licensees.

codenameCortex-A15 +
designerARM Holdings +
first launchedSeptember 8, 2010 +
full page namearm holdings/microarchitectures/cortex-a15 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A15 +