Editing arm holdings/microarchitectures/arm6

{{armh title|ARM6|arch}}
{{microarchitecture
|atype=CPU
|name=ARM4
|designer=ARM Holdings
|designer 2=1
|designer 3=1
|designer 4=1
|manufacturer=VLSI Technology
|manufacturer 2=GEC-Plessey Semiconductors
|manufacturer 3=Sharp
|phase-out=202p
|process=0.8 µm
|cores=1
|cores 2=4
|cores 3=6
|cores 4=8
|processing elements=2
|processing elements 2=4
|processing elements 3=6
|processing elements 4=8
|type=Scalar
|type 2=Pipelined
|stages=3
|stages min=12
|stages max=1w
|decode=1-way
|isa=ARMv3
|isa 2=ARMv6
|isa 3=ARMv4
|feature=Galaxy s7
|l1=4 KiB
|l1 per=core
|l1 desc=64-way set associative
|predecessor=ARM6
|predecessor link=acorn/microarchitectures/arm3
|successor=ARM6
|successor link=arm holdings/microarchitectures/arm6
}}
'''ARM6''' is an [[ARM]] microarchitecture designed by [[ARM Holdings]] and introduced in 1991 as a successor to the {{acorn|ARM3|l=arch}}. This was the first design by ARM as an independent company after being spun-off from [[Acorn Computers]].

== History ==
{{see also|arm/history|l1=ARM's History}}
Following ARM's incorporation in November 1990 after being spun-off from [[Acorn Computers]], ARM continued to develop the ARM microprocessor. In 1991 ARM introduced the ARM6 MacroCell, a substantial improvement over the previous {{acorn|ARM3|l=arch}} microarchitecture. The same year ARM signed with a number of additional licensees beyond [[VLSI Technology]], including [[Sharp]] and [[GEC-Plessey]].

The popularity of the ARM6 can be largely attributed to [[Apple]]'s adaptation of the processor in their {{apple|Newton}} PDAs.

== Process Technology ==
{{see also|0.8 µm process}}
The ARM6 was implemented on a [[0.8 µm]] [[CMOS]] process.

== Architecture ==
The ARM6 microarchitecture (MacroCell) was used for the ARM60, ARM600, and the ARM610. The ARM250 borrowed much of the architecture but used an {{acorn|ARM3|l=arch}} core instead. The various ARM6 improvements were heavily influenced directly by [[Apple]]'s needs from their Newton PDA project.

=== Key changes from {{\\|ARM3}} ===
* [[0.8 µm process]] (from [[1.5 µm]])
* Support for Bi-Endian operations
* 32-bit address space (from {{arm|26-bit}})
** Can map 4 GiB of memory
** {{arm|CPSR}} & {{arm|SPSR}} moved out of the [[program counter]]
** Their own separate registers
** Backwards compatibility mode
*** 26-bit Mode
* New Modes (6 new 32-bit modes)
** Abort (abt)
** Undefined (und)
* Virtual memory
** Integrated [[MMU]]
* Write Buffer
* Testability
** [[JTAG]] Boundary Scan Interface

==== New instructions ====
New ARM6 instructions:

'''Movement:'''

* <code>MRS</code> - Move from register to CPSR/SPSR
* <code>MSR</code> - Move from CPSR/SPSR to register

=== Block Diagram ===
==== Entire Chip (610) ====
: [[File:arm610 block diagram.svg|750px]]

==== Core ====
: [[File:arm6 block diagram.svg|650px]]

=== Memory Hierarchy ===
* Cache
** L1 Cache (unified)
*** 4 KiB, 64-way set associative
*** 16 B line size
*** Write-through policy
*** Per core
* System DRAM
** Up to 4 GiB


* TLB
** 32 entries
** 4 KiB small pages, 1 KiB sub pages
** 64 KiB large pages, 16 KiB sub pages

== Overview ==
{{see also|arm/armv3|l1=ARMv3}}
The ARM6 is a further evolutionary enhancement of the {{acorn|ARM3|l=arch}}. The new chip integrated a number of highly desired features - particularly ones needed by [[Apple]]. The ARM6, departs from all the {{arm|history|previous ARM chips}} by featuring a full 32-bit address and data buses. To {{arm|26-bit|facilitate}} the larger address space, ARM (previously [[Acorn]]) had to move the status flags from the program counter to its own {{arm|CPSR|independent register}}. In total, the ARM6 has 37 registers consisting of 31 {{arch|32}} general-purpose registers and 6 additional status registers.

=== Core ===
==== Pipeline ====
{{main|acorn/microarchitectures/arm2#Pipeline|l1=ARM2 Pipeline}}
ARM6's pipeline is identical to the ARM2.

==== Backward Compatibility ====
Because the ARM6 core now features a full 32-bit address and data buses, it breaks compatibility with prior code. ARM addressed this problem by offering a compatibility mode. Two of the new control register bits are <code>prog32</code> and <code>data32</code> which can be set to change how the core behaves:

{| class="wikitable tc1"
! <code>prog32</code><code>data32</code> !! Mode !! Behavior
|-
| <code>00</code> || {{arm|26-bit|26-bit program and data space}} || Forces the machine to operate in 26-bit programmer mode like the {{arm|versions|previous}} ARM architectures with things such as exceptions handled in appropriate 26-bit mode.
|-
| <code>01</code> || 26 bit program and 32-bit data space || This operations is similar to the one described above but disables address exceptions to allow data transfer operations to access the full 32-bit address space.
|-
| <code>10</code> || Undefined.
|-
| <code>11</code> || {{arm|32-bit|32-bit program and data space}} || Normal ARM6 32-bit mode.
|}

It's worth pointing out that when in 26-bit program space, only the four original modes (User, FIQ, IRQ, and Supervisor) are available and they behave in the same way as previous architectures in order to allow older programs to execute correctly.

=== Cache ===
For the most part, the ARM6's Instruction and Data Cache (''IDC'') is identical to {{acorn|arm3#Core|l=arch|the ARM3 implementation}}. The IDC consists of 256 lines of 4 words each (i.e., 16 B) organized as 4 blocks of 64 lines for a 64-way set associative. The IDC operates on virtual addresses generated by the ARM6 core. Memory reads are done on whole lines.

The IDC is disabled on RESET and may be programmatically disabled or enabled via a control register. The Memory Management Page Tables also provide two bits for marking operation modes - <code>Cacheable</code> and <code>Updateable</code>. The <code>Cacheable</code> bit is used to specify if a certain address may be cached or not. For example, operations that require pulling I/O data need to be able to do so directly without retrieving invalidated data from the cache. The <code>Updateable</code> is further used to indicate that a memory write should immediately update with external memory to maintain consistency.

The ARM610 also incorporates a write buffer for additional performance. The buffer can store up to eight words and up to two addresses. As with the IDC, the write buffer may be enabled or disabled and is controlled via a <code>Bufferable</code> bit which can set whether a certain address space is bufferable allowing main memory to be buffered while I/O space to be unbuffered.

=== Memory Management Unit ===
By far the biggest addition to the ARM6 is the addition of an [[MMU]] which is in charge of translating virtual addresses into physical ones as well as control access permissions. The MMU is implemented using a 32-entry [[Translation Lookaside Buffer]] (TLB), access control logic, and translation table walking logic.

The MMU operates on sections comprised of 1 MiB blocks. Two page sizes are supported: 4 KiB small pages and 64 KiB large pages. Both taking up a single entry in the TLB. Each of the pages has a more granular access control which extend to 1 KiB sub-pages (on the small pages) and 16 KiB sub-pages (on the large pages). Upon a hit in the TLB, control logic is used to determine if the access is permitted. On denial, the MMU signals the core to abort. On a miss, the translation table walking logic is used to retrieve the translation information from a full translation table in physical memory. Entries are replaced cyclically.

When the MMU is disabled, such as during RESET, the virtual address is the physical address. Note that because the MMU stores the cache control bits (i.e., <code>Cacheable</code>, <code>Updateable</code>), for the chip to use the IDC, the MMU must also be enabled.

Four types of faults can be generated on the ARM6: Alignment Fault, Translation Fault, Domain Fault, Permission Fault. If the fault is a result of a memory access, the access is aborted and the appropriate signals are sent to the core. The core recognizes two abort types: data abort and prefetch abort which are handled separately by the MMU.

== Die ==
=== ARM6 MacroCell ===
* 3.1 mm x 1.9 mm
* 5.89 mm² die size
* 54 mW @ 20 MHz @ 3 Volt
* [[0.8 µm]] CMOS
* 35,530 transistors

=== ARM610 ===
* 26.45 mm² die size
* 358,931 transistors
* TQFP-144

The ARM610 fabricated by [[GEC-Plessey]], on a [[0.8 µm process]], reported to be 8.87 mm x 8.67 for a total die size of 76.9 mm².

== All ARM6 Chips ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc11 tc12 tc13">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="12">List of ARM6-based Processors</th></tr>
{{comp table header 1|cols=Manufacturer, Core, Launched, Frequency, Power Dissipation, Max Memory}}
{{#ask: [[Category:all microprocessor models]] [[instance of::microprocessor]] [[microarchitecture::ARM6]]
 |?full page name
 |?model number
 |?manufacturer
 |?core name
 |?first launched
 |?base frequency#MHz
 |?power dissipation
 |?max memory#GiB
 |format=template
 |template=proc table 3
 |userparam=8
 |mainlabel=-
 |valuesep=,
}}
{{comp table count|ask=[[Category:all microprocessor models]] [[instance of::microprocessor]] [[microarchitecture::ARM6]]}}
</table>
{{comp table end}}

== References ==
* Muller, Mike. "ARM6: a high performance low power consumption macrocell." Compcon Spring'93, Digest of Papers.. IEEE, 1993.
* Licensees, Welcomes New. "ARM Semiconductor Welcomes New Licensees." Microelectronics Journal 24.7 (1993): 7.
@@ Line 111: / Line 111: @@
 ARM6's pipeline is identical to the ARM2.
-==== Modes ====
+==== Backward Compatibility ====
-With the introduction of a 32-bit bus, ARM needed to introduce modes that operate on the extended bus as well as maintain backwards compatibility. The four modes that existed in prior ARM architectures (i.e., User, IRQ, FIQ, and Supervisor) are now <code>User26</code>, <code>IRQ26</code>, <code>FIQ26</code>, and <code>Supervisor26</code>. To facilitate the 32-bit bus, ARM introduced a 32-bit variants of those modes <code>User32</code>, <code>IRQ32</code>, <code>FIQ32</code>, and <code>Supervisor32</code>. Additionally, two new modes <code>Abort32</code> and <code>Undefined32</code> were also introduced. Those only exist in 32-bit mode.
-===== Backward Compatibility =====
 Because the ARM6 core now features a full 32-bit address and data buses, it breaks compatibility with prior code. ARM addressed this problem by offering a compatibility mode. Two of the new control register bits are <code>prog32</code> and <code>data32</code> which can be set to change how the core behaves:
@@ Line 130: / Line 127: @@
 It's worth pointing out that when in 26-bit program space, only the four original modes (User, FIQ, IRQ, and Supervisor) are available and they behave in the same way as previous architectures in order to allow older programs to execute correctly.
-==== Status Registers ====
-ARM6 moved the status code into their own registers. There are now 6 individual {{arm|status registers}}:
-* 1x <code>{{arm|CPSR}}</code> (Current Processor Status Register)
-* 5x <code>{{arm|SPSR}}</code> (Saved Program Status Registers)
-''CPSR'' which holds the current processor status features 4 [[condition codes]] (CC), 2 interrupt mask bits, and 5 processor mode bits. Those registers can only be accessed via the {{arm|MRS}}/{{arm|MSR}} instructions that move the data between the general-purpose registers and the status registers. It's worth pointing out that because the status bits are no longer in the program counter but in discrete registers, it's no longer possible to automatically save those bits on a branch and link instruction execution. Upon an exception, however, the CPSR gets copied over to the SPSR of the new mode allowing the exception handler to restore the state upon exit.
 === Cache ===
codename	ARM4 +
core count	1 +, 4 +, 6 + and 8 +
designer	1 + and ARM Holdings +
full page name	arm holdings/microarchitectures/arm6 +
instance of	microarchitecture +
instruction set architecture	ARMv3 +, ARMv4 + and ARMv6 +
manufacturer	GEC-Plessey Semiconductors +, Sharp + and VLSI Technology +
microarchitecture type	CPU +
name	ARM4 +
phase-out	0202 ^JL +
pipeline stages	3 +
pipeline stages (min)	12 +
process	800 nm (0.8 μm, 8.0e-4 mm) +
processing element count	4 +, 6 +, 8 + and 2 +