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By far the biggest addition to the ARM6 is the addition of an [[MMU]] which is in charge of translating virtual addresses into physical ones as well as control access permissions. The MMU is implemented using a 32-entry [[Translation Lookaside Buffer]] (TLB), access control logic, and translation table walking logic. | By far the biggest addition to the ARM6 is the addition of an [[MMU]] which is in charge of translating virtual addresses into physical ones as well as control access permissions. The MMU is implemented using a 32-entry [[Translation Lookaside Buffer]] (TLB), access control logic, and translation table walking logic. | ||
− | The MMU operates on sections comprised of 1 MiB blocks. Two page sizes are supported: 4 KiB small pages and 64 KiB large pages. Both taking up a single entry in the TLB. Each of the pages has a more granular access control which extend to 1 KiB sub-pages (on the small pages) and 16 KiB sub-pages (on the large pages) | + | The MMU operates on sections comprised of 1 MiB blocks. Two page sizes are supported: 4 KiB small pages and 64 KiB large pages. Both taking up a single entry in the TLB. Each of the pages has a more granular access control which extend to 1 KiB sub-pages (on the small pages) and 16 KiB sub-pages (on the large pages). |
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Four types of faults can be generated on the ARM6: Alignment Fault, Translation Fault, Domain Fault, Permission Fault. If the fault is a result of a memory access, the access is aborted and the appropriate signals are sent to the core. The core recognizes two abort types: data abort and prefetch abort which are handled separately by the MMU. | Four types of faults can be generated on the ARM6: Alignment Fault, Translation Fault, Domain Fault, Permission Fault. If the fault is a result of a memory access, the access is aborted and the appropriate signals are sent to the core. The core recognizes two abort types: data abort and prefetch abort which are handled separately by the MMU. |
Facts about "ARM6 - Microarchitectures - ARM"
codename | ARM4 + |
core count | 1 +, 4 +, 6 + and 8 + |
designer | 1 + and ARM Holdings + |
full page name | arm holdings/microarchitectures/arm6 + |
instance of | microarchitecture + |
instruction set architecture | ARMv3 +, ARMv4 + and ARMv6 + |
manufacturer | GEC-Plessey Semiconductors +, Sharp + and VLSI Technology + |
microarchitecture type | CPU + |
name | ARM4 + |
phase-out | 0202 JL + |
pipeline stages | 3 + |
pipeline stages (min) | 12 + |
process | 800 nm (0.8 μm, 8.0e-4 mm) + |
processing element count | 4 +, 6 +, 8 + and 2 + |