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{{armh title|Neoverse N1|arch}}
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{{microarchitecture
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|atype=CPU
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|name=Neoverse N1
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|designer=ARM Holdings
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|manufacturer=TSMC
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|introduction=February 20, 2019
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|process=7 nm
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|cores=4
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|cores 2=8
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|cores 3=16
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|cores 4=32
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|cores 5=64
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|cores 6=96
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|cores 7=128
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|type=Superscalar
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|type 2=Superpipeline
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|oooe=Yes
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|speculative=Yes
 +
|renaming=Yes
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|stages=11
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|decode=4-way
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|isa=ARMv8.2
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|l1i=64 KiB
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|l1i per=core
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|l1i desc=4-way set associative
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|l1d=64 KiB
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|l1d per=core
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|l1d desc=4-way set associative
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|l2=512-1 MiB
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|l2 per=core
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|l2 desc=8-way set associative
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|l3=2-4 MiB
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|l3 per=core duplex
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|l3 desc=16-way set associative
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|predecessor=Cosmos
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|predecessor link=arm_holdings/cosmos
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|successor=Zeus
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|successor link=arm_holdings/microarchitectures/zeus
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}}
 +
'''Neoverse N1''' (codename '''Ares''') is a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
  
 +
== History ==
 +
[[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]]
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The Neoverse N1, formerly Ares, is the first [[Arm]] design to specifically target the infrastructure market, serving as the successor to the {{armh|Cosmos|Cosmos platform}} which used the same cores as the client platform. The N1 was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote. Ares was officially unveiled on February 20, 2019.
 +
 +
== Release Dates ==
 +
Ares was officially disclosed on February 20, 2019.
 +
 +
== Process Technology ==
 +
Ares specifically takes advantage of the power and area advantages of the [[7 nm process]].
 +
 +
== Architecture ==
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The Neoverse N1 core is almost identical to the {{\\|Cortex-A76}} but features a number of enhancements for infrastructure workload.
 +
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* [[7 nm process]]
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* Core
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** 11-stage
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** 4-way decode
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** 8-way issue
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* System architecture
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** Designed for the [[Coherent Mesh Network 600]] (CMN-600) mesh interconnect
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=== Block Diagram ===
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==== Typical SoC ====
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:[[File:neoverse n1 soc block diagram.svg|850px]]
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 +
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The Neoverse N1 is also expected to be integrated along with {{\\|Neoverse E1}} high-efficiency cores and possibly other custom IP blocks.
 +
 +
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:[[File:neoverse e1 n1 soc example.svg|750px]]
 +
 +
==== Individual Core ====
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:[[File:neoverse n1 block diagram.svg|850px]]
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 +
=== Memory Hierarchy ===
 +
The Neoverse N1 has a private L1I, L1D, and L2 cache.
 +
 +
* Cache
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** L1I Cache
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*** 64 KiB, 4-way set associative
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*** 64-byte cache lines
 +
*** SECDED ECC
 +
*** Write-back
 +
** L1D Cache
 +
*** 64 KiB, 4-way set associative
 +
*** 64-byte cache lines
 +
*** 4-cycle fastest load-to-use latency
 +
*** SECDED ECC
 +
*** Write-back
 +
** L2 Cache
 +
*** 512 KiB OR 1 MiB (2 banks)
 +
*** 8-way set associative
 +
*** 9-11 cycle
 +
**** 9-cycle fastest load-to-use latency
 +
*** ECC protection per 64 bits
 +
*** [[Modified Exclusive Shared Invalid]] (MESI) coherency
 +
*** Strictly inclusive of the L1 data cache & non-inclusive of the L1 instruction cache
 +
*** Write-back
 +
** System-level cache (SLC)
 +
*** 1 Bank per core duplex
 +
*** 2 MiB to 4 MiB, 16-way set associative
 +
 +
The Neoverse N1 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB).
 +
 +
* TLBs
 +
** ITLB
 +
*** 4 KiB, 16 KiB, 64 KiB, 2 MiB, and 32 MiB page sizes
 +
*** 48-entry fully associative
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** DTLB
 +
*** 48-entry fully associative
 +
*** 4 KiB, 16 KiB, 64 KiB, 2 MiB, and 512 MiB page sizes
 +
** STLB
 +
*** 1280-entry 5-way set associative
 +
 +
== Overview ==
 +
[[File:neoverse n1 overview.svg|right|500px|thumb|Neoverse N1 Typical SoC]]
 +
Formerly known as Ares, the Neoverse N1 is the first ground-up Arm microarchitecture design that targets infrastructure, targetting a wide range of markets from the [[edge computing|edge]] to [[hyperscalers]] data centers. Departing from Arm's low-power {{armh|cortex|mobile cores}}, the N1 targets high-performance server workloads at higher TDPs and higher compute power. Compared to the prior {{armh|Cosmos|l=arch}} platform, the Neoverse N1 is said to deliver a significant uplift in single-thread performance.
 +
 +
The Neoverse N1 is designed to enable Arm partners rapid development of high-performance server products. The N1 features an 11-stage [[out-of-order]] core with private [[L1]] and [[L2]] caches. The core is intended to leverage Arm's {{armh|Coherent Mesh Network}} 600 (CMN-600) [[interconnect]] to scale from as little as a [[quad-core]] design to as much as [[128 cores]] and from a single [[DDR]] channel all the way up to eight channels, depending on the kind of workload being addressed. Extending the base design is a framework for [[multiprocessing]] support as well as [[chiplets]] support which can be used by companies who are looking to improve [[yield]] and manufacturability with large SoC designs. The N1 is also designed to work seamlessly with the {{\\|Neoverse E1}} which was introduced at the same time as N1 but is optimized for high throughput multithreaded workloads.
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== Core ==
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The Neoverse N1 features an 11-stage accordion integer pipeline.
 +
 +
 +
::[[File:neoverse n1 pipeline.svg|600px]]
 +
 +
== Die ==
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=== N1 core ===
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* [[7 nm process]]
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* 1 Core + L2
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* 1.2 mm² die size (1C + 512 KiB L2)
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* 1.4 mm² die size (1C + 1 MiB L2)
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* 1 W @ 2.6 GHz (0.75 V), 1.8 W @ 3.1 GHz (1.0 V)
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 +
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:[[File:neoverse n1 core die plot.png|600px]]
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== All Neoverse N1 Processors ==
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<!-- NOTE:
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          This table is generated automatically from the data in the actual articles.
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          If a microprocessor is missing from the list, an appropriate article for it needs to be
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          created and tagged accordingly.
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          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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-->
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{{comp table start}}
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<table class="comptable sortable tc4 tc6 tc9">
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{{comp table header|main|8:List of Neoverse N1-based Processors}}
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{{comp table header|cols|Family|Launched|Process|Arch|Cores|%Frequency}}
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{{#ask: [[Category:all microprocessor models]] [[microarchitecture::Neoverse N1]]
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|?full page name
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|?model number
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|?family
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|?first launched
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|?process
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|?microarchitecture
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|?core count
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|?base frequency#GHz
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|format=template
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|template=proc table 3
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|userparam=8
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|mainlabel=-
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|valuesep=,
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}}
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{{comp table count|ask=[[Category:all microprocessor models]] [[microarchitecture::Neoverse N1]]}}
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</table>
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{{comp table end}}
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== Bibliography ==
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* Drew Henry keynote, TechCon 2018 keynote.
 +
* Drew Henry, direct communication
 +
* Most of the technical details were obtained directly from Arm

Revision as of 23:06, 23 March 2020

Edit Values
Neoverse N1 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionFebruary 20, 2019
Process7 nm
Core Configs4, 8, 16, 32, 64, 96, 128
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages11
Decode4-way
Instructions
ISAARMv8.2
Cache
L1I Cache64 KiB/core
4-way set associative
L1D Cache64 KiB/core
4-way set associative
L2 Cache512-1 MiB/core
8-way set associative
L3 Cache2-4 MiB/core duplex
16-way set associative
Succession

Neoverse N1 (codename Ares) is a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

History

Arm's server roadmap.

The Neoverse N1, formerly Ares, is the first Arm design to specifically target the infrastructure market, serving as the successor to the Cosmos platform which used the same cores as the client platform. The N1 was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote. Ares was officially unveiled on February 20, 2019.

Release Dates

Ares was officially disclosed on February 20, 2019.

Process Technology

Ares specifically takes advantage of the power and area advantages of the 7 nm process.

Architecture

The Neoverse N1 core is almost identical to the Cortex-A76 but features a number of enhancements for infrastructure workload.

Block Diagram

Typical SoC

neoverse n1 soc block diagram.svg


The Neoverse N1 is also expected to be integrated along with Neoverse E1 high-efficiency cores and possibly other custom IP blocks.


neoverse e1 n1 soc example.svg

Individual Core

neoverse n1 block diagram.svg

Memory Hierarchy

The Neoverse N1 has a private L1I, L1D, and L2 cache.

  • Cache
    • L1I Cache
      • 64 KiB, 4-way set associative
      • 64-byte cache lines
      • SECDED ECC
      • Write-back
    • L1D Cache
      • 64 KiB, 4-way set associative
      • 64-byte cache lines
      • 4-cycle fastest load-to-use latency
      • SECDED ECC
      • Write-back
    • L2 Cache
      • 512 KiB OR 1 MiB (2 banks)
      • 8-way set associative
      • 9-11 cycle
        • 9-cycle fastest load-to-use latency
      • ECC protection per 64 bits
      • Modified Exclusive Shared Invalid (MESI) coherency
      • Strictly inclusive of the L1 data cache & non-inclusive of the L1 instruction cache
      • Write-back
    • System-level cache (SLC)
      • 1 Bank per core duplex
      • 2 MiB to 4 MiB, 16-way set associative

The Neoverse N1 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB).

  • TLBs
    • ITLB
      • 4 KiB, 16 KiB, 64 KiB, 2 MiB, and 32 MiB page sizes
      • 48-entry fully associative
    • DTLB
      • 48-entry fully associative
      • 4 KiB, 16 KiB, 64 KiB, 2 MiB, and 512 MiB page sizes
    • STLB
      • 1280-entry 5-way set associative

Overview

Neoverse N1 Typical SoC

Formerly known as Ares, the Neoverse N1 is the first ground-up Arm microarchitecture design that targets infrastructure, targetting a wide range of markets from the edge to hyperscalers data centers. Departing from Arm's low-power mobile cores, the N1 targets high-performance server workloads at higher TDPs and higher compute power. Compared to the prior Cosmos platform, the Neoverse N1 is said to deliver a significant uplift in single-thread performance.

The Neoverse N1 is designed to enable Arm partners rapid development of high-performance server products. The N1 features an 11-stage out-of-order core with private L1 and L2 caches. The core is intended to leverage Arm's Coherent Mesh Network 600 (CMN-600) interconnect to scale from as little as a quad-core design to as much as 128 cores and from a single DDR channel all the way up to eight channels, depending on the kind of workload being addressed. Extending the base design is a framework for multiprocessing support as well as chiplets support which can be used by companies who are looking to improve yield and manufacturability with large SoC designs. The N1 is also designed to work seamlessly with the Neoverse E1 which was introduced at the same time as N1 but is optimized for high throughput multithreaded workloads.

Core

The Neoverse N1 features an 11-stage accordion integer pipeline.


neoverse n1 pipeline.svg

Die

N1 core

  • 7 nm process
  • 1 Core + L2
  • 1.2 mm² die size (1C + 512 KiB L2)
  • 1.4 mm² die size (1C + 1 MiB L2)
  • 1 W @ 2.6 GHz (0.75 V), 1.8 W @ 3.1 GHz (1.0 V)


neoverse n1 core die plot.png

All Neoverse N1 Processors

 List of Neoverse N1-based Processors
ModelFamilyLaunchedProcessArchCoresFrequency
ALC12B00Graviton3 December 20197 nm
0.007 μm
7.0e-6 mm
Neoverse N1642.5 GHz
2,500 MHz
2,500,000 kHz
Count: 1

Bibliography

  • Drew Henry keynote, TechCon 2018 keynote.
  • Drew Henry, direct communication
  • Most of the technical details were obtained directly from Arm
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/neoverse_n1&oldid=96487"
Facts about "Neoverse N1 - Microarchitectures - ARM"
RDF feed
codenameNeoverse N1 +
core count4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 +
designerARM Holdings +
first launchedFebruary 20, 2019 +
full page namearm holdings/microarchitectures/neoverse n1 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +
microarchitecture typeCPU +
nameNeoverse N1 +
pipeline stages11 +
process7 nm (0.007 μm, 7.0e-6 mm) +