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{{arm title|Memory Tagging Extension (MTE)}}{{arm isa main}}
 
{{arm title|Memory Tagging Extension (MTE)}}{{arm isa main}}
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'''Memory tagging extension''' ('''MTE''') is an [[ARM]] {{arm|extension}} that enables hardware [[memory tagging]]. MTE was introduced with the {{arm|ARMv8.5}} ISA.
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'''Memory tagging extension''' ('''MTE''', '''MemTag''', '''ARMv8.5-MemTag''') is an [[ARM]] {{arm|extension}} that enables hardware-assisted [[memory tagging]]. MTE was introduced with the {{arm|ARMv8.5}} ISA. MTE is an optional extension.
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== Overview ==
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The {{arm|ARMv8.5}} ISA introduces the memory Tagging Extension (MTE) which allows tags to be assigned to each memory allocation. Consequently, all memory accesses must then be made via a pointer with the correct tag. Memory accesses that use incorrect tags will trap, allowing the operating system to choose the course of action. MTE uses a 4-bit tag for every 16 bytes of memory. It's worth noting that the MTE pointer tags use the existing ARM ISA feature that is also used by the {{arm|Pointer Authentication}} (PA) extension. This means that when both features are enabled, the {{arm|PAC}} size is reduced by eight bits to accommodate MTE.
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== Instructions ==
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MTE introduces 16 new instructions for working with tagged memory:
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{| class="wikitable"
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|-
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! Instruction !! Name !! Format
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|-
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| <code>ADDG</code> || Add with Tag || <code>ADDG <Xd/SP>, <Xn/SP>, #<uimm6>, #<uimm4></code>
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|-
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| <code>CMPP</code> || Compare with Tag || <code>CMPP <Xn/SP>, <Xm/SP></code>
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|-
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| <code>GMI</code> || Tag Mask Insert || <code>GMI <Xd>, <Xn/SP>, <Xm></code>
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|-
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| <code>IRG</code> || Insert Random Tag || <code>IRG <Xd/SP>, <Xn/SP>{, <Xm>}</code>
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|-
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| <code>LDG</code> || Load Allocation Tag || <code>LDG <Xt>, [<Xn/SP>{, #<simm>}]</code>
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|-
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| <code>LDGV</code> || Load Tag Vector || <code>LDGV <Xt>, [<Xn/SP>]!</code>
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|-
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| <code>ST2G</code> || Store Allocaton Tags || <code>ST2G [<Xn/SP>], #<simm></code><br><code>ST2G [<Xn/SP>, #<simm>]!</code>
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|-
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| <code>STG</code> || Store Allocation Tag || <code>STG [<Xn/SP>], #<simm></code><br><code>STG [<Xn/SP>, #<simm>]!</code><br><code>STG [<Xn/SP>{, #<simm>}]</code>
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|-
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| <code>STGP</code> || Store Allocation Tag and Pair || <code>STGP <Xt1>, <Xt2>, [<Xn/SP>], #<imm></code><br><code>STGP <Xt1>, <Xt2>, [<Xn/SP>, #<imm>]!</code><br><code>STGP <Xt1>, <Xt2>, [<Xn/SP>{, #<imm>}]</code>
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|-
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| <code>STGV</code> || Store Tag Vector || <code>STGV <Xt>, [<Xn/SP>]!</code>
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|-
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| <code>STZ2G</code> || Store Allocation Tags, Zeroing || <code>STZ2G [<Xn/SP>], #<simm></code><br><code>STZ2G [<Xn/SP>, #<simm>]!</code><br><code>STZ2G [<Xn/SP>{, #<simm>}]</code>
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|-
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| <code>STZG</code> || Store Allocation Tag, Zeroing || <code>STZG [<Xn/SP>], #<simm></code><br><code>STZG [<Xn/SP>, #<simm>]!</code><br><code>STZG [<Xn/SP>{, #<simm>}]</code>
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|-
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| <code>SUBG</code> || Subtract with Tag || <code>SUBG <Xd/SP>, <Xn/SP>, #<uimm6>, #<uimm4></code>
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|-
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| <code>SUBP</code> || Subtract Pointer || <code>SUBP <Xd>, <Xn/SP>, <Xm/SP></code>
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|-
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| <code>SUBPS</code> || Subtract Pointer, setting Flags || <code>SUBPS <Xd>, <Xn/SP>, <Xm/SP></code>
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|}
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== See also ==
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* SPARC's {{sparc|Application Data Integrity}} (ADI)
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* ARM's {{arm|Top-byte Ignore}} (TBI)
  
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{{stub}}
 
 
[[category:arm]]
 
[[category:arm]]

Latest revision as of 05:49, 12 July 2019

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Memory tagging extension (MTE, MemTag, ARMv8.5-MemTag) is an ARM extension that enables hardware-assisted memory tagging. MTE was introduced with the ARMv8.5 ISA. MTE is an optional extension.

Overview[edit]

The ARMv8.5 ISA introduces the memory Tagging Extension (MTE) which allows tags to be assigned to each memory allocation. Consequently, all memory accesses must then be made via a pointer with the correct tag. Memory accesses that use incorrect tags will trap, allowing the operating system to choose the course of action. MTE uses a 4-bit tag for every 16 bytes of memory. It's worth noting that the MTE pointer tags use the existing ARM ISA feature that is also used by the Pointer Authentication (PA) extension. This means that when both features are enabled, the PAC size is reduced by eight bits to accommodate MTE.

Instructions[edit]

MTE introduces 16 new instructions for working with tagged memory:

Instruction Name Format
ADDG Add with Tag ADDG <Xd/SP>, <Xn/SP>, #<uimm6>, #<uimm4>
CMPP Compare with Tag CMPP <Xn/SP>, <Xm/SP>
GMI Tag Mask Insert GMI <Xd>, <Xn/SP>, <Xm>
IRG Insert Random Tag IRG <Xd/SP>, <Xn/SP>{, <Xm>}
LDG Load Allocation Tag LDG <Xt>, [<Xn/SP>{, #<simm>}]
LDGV Load Tag Vector LDGV <Xt>, [<Xn/SP>]!
ST2G Store Allocaton Tags ST2G [<Xn/SP>], #<simm>
ST2G [<Xn/SP>, #<simm>]!
STG Store Allocation Tag STG [<Xn/SP>], #<simm>
STG [<Xn/SP>, #<simm>]!
STG [<Xn/SP>{, #<simm>}]
STGP Store Allocation Tag and Pair STGP <Xt1>, <Xt2>, [<Xn/SP>], #<imm>
STGP <Xt1>, <Xt2>, [<Xn/SP>, #<imm>]!
STGP <Xt1>, <Xt2>, [<Xn/SP>{, #<imm>}]
STGV Store Tag Vector STGV <Xt>, [<Xn/SP>]!
STZ2G Store Allocation Tags, Zeroing STZ2G [<Xn/SP>], #<simm>
STZ2G [<Xn/SP>, #<simm>]!
STZ2G [<Xn/SP>{, #<simm>}]
STZG Store Allocation Tag, Zeroing STZG [<Xn/SP>], #<simm>
STZG [<Xn/SP>, #<simm>]!
STZG [<Xn/SP>{, #<simm>}]
SUBG Subtract with Tag SUBG <Xd/SP>, <Xn/SP>, #<uimm6>, #<uimm4>
SUBP Subtract Pointer SUBP <Xd>, <Xn/SP>, <Xm/SP>
SUBPS Subtract Pointer, setting Flags SUBPS <Xd>, <Xn/SP>, <Xm/SP>

See also[edit]

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